CYWUSB6935 Cypress Semiconductor Corporation., CYWUSB6935 Datasheet - Page 18

• Manufacturer Part Number: CYWUSB6935
• Description: Lr 2.4-ghz Dsss Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

Note:
Document #: 38-16008 Rev. *D
Bit
7:6 Reserved
5
4:0 RSSI
Bit
7:3
2:0
Bit
7
6
5:0 Crystal Adjust
6.
Reserved
The RSSI will collect a single value each time the part is put into receive mode via Control register (Reg 0x03, bit 7=1). See Section 4.7 for more details.
Name
Valid
Name
Reserved
Clock Output Disable The Clock Output Disable bit disables the 13-MHz clock driven on the X13OUT pin.
Name
Reserved
PA Bias
7
7
7
Addr: 0x22
Addr: 0x23
Addr: 0x24
Reserved
Description
These bits are reserved. This register is read-only.
The Valid bit indicates whether the RSSI value in bits [4:0] are valid. This register is Read Only.
The Receive Strength Signal Indicator (RSSI) value indicates the strength of the received signal. This is a read only value
with the higher values indicating stronger received signals meaning more reliable transmissions.
Description
These bits are reserved and should be written with zeroes.
The Power Amplifier Bias (PA Bias) bits are used to set the transmit power of the IC through increasing (values up to 7) or
decreasing (values down to 0) the gain of the on-chip Power Amplifier. The higher the register value the higher the transmit
power. By changing the PA Bias value signal strength management functions can be accomplished. For general purpose
communication a value of 7 is recommended. See Table 4-1 for typical output power steps based on the PA Bias bit settings.
Clock Output
1 = RSSI value is valid
0 = RSSI value is invalid
Disable
6
6
6
Description
This bit is reserved and should be written with zero.
If the 13-MHz clock is driven on the X13OUT pin then receive sensitivity will be reduced by –4 dBm on channels
5+13n. By default the 13-MHz clock output pin is enabled. This pin is useful for adjusting the 13-MHz clock, but it
interfere with every 13th channel beginning with 2.405-GHz channel. Therefore, it is recommended that the 13-MHz
clock output pin be disabled when not in use.
The Crystal Adjust value is used to calibrate the on-chip parallel load capacitance supplied to the crystal. Each
increment of the Crystal Adjust value typically adds 0.135 pF of parallel load capacitance. The total range is 8.5 pF,
starting at 8.65 pF. These numbers do not include PCB parasitics, which can add an additional 1–2 pF.
1 = No 13-MHz clock driven externa
0 = 13-MHz clock driven externally
Figure 7-23. Receive Signal Strength Indicator (RSSI)
Reserved
Valid
5
5
5
Figure 7-25. Crystal Adjust
REG_CRYSTAL_ADJ
Figure 7-24. PA Bias
4
4
4
REG_RSSI
REG_PA
ll
y
3
3
3
Crystal Adjust
RSSI
2
2
2
[6]
PA Bias
1
1
1
CYWUSB6935
Default: 0x00
Default: 0x00
Default: 0x00
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