CYWUSB6935 Cypress Semiconductor Corporation., CYWUSB6935 Datasheet - Page 3

• Manufacturer Part Number: CYWUSB6935
• Description: Lr 2.4-ghz Dsss Radio Soc
• Manufacturer: Cypress Semiconductor Corporation.

An optional SERDES Bypass mode (DIO) is provided for appli-
cations that require a synchronous serial bit-oriented data
path. This interface is for data only.
4.6
A 13-MHz crystal is directly connected to X13IN and X13
without the need for external capacitors. The CYWUSB6935
has a programmable trim capability for adjusting the on-chip
load capacitance supplied to the crystal. The Radio Frequency
(RF) circuitry has on-chip decoupling capacitors. The
CYWUSB6935 is powered from a 2.7V to 3.6V DC supply. The
CYWUSB6935 can be shutdown to a fully static state using the
PD pin.
Below are the requirements for the crystal to be directly
connected to X13IN and X13:
4.7
The RSSI register (Reg 0x22) returns the relative signal
strength of the ON-channel signal power and can be used to:
The internal RSSI voltage is sampled through a 5-bit
analog-to-digital converter (ADC). A state machine controls
the conversion process. Under normal conditions, the RSSI
state machine initiates a conversion when an ON-channel
carrier is detected and remains above the noise floor for over
50 µs. The conversion produces a 5-bit value in the RSSI
register (Reg 0x22, bits 4:0) along with a valid bit, RSSI
register (Reg 0x22, bit 5). The state machine then remains in
HALT mode and does not reset for a new conversion until the
receive mode is toggled off and on. Once a connection has
been established, the RSSI register can be read to determine
the relative connection quality of the channel. A RSSI register
value lower than 10 indicates that the received signal strength
is low, a value greater than 28 indicates a strong signal level.
To check for a quiet channel before transmitting, first set up
receive mode properly and read the RSSI register (Reg 0x22).
If the valid bit is zero, then force the Carrier Detect register
(Reg 0x2F, bit 7=1) to initiate an ADC conversion. Then, wait
greater than 50 µs and read the RSSI register again. Next,
Document #: 38-16008 Rev. *D
1. Determine the connection quality
2. Determine the value of the noise floor
3. Check for a quiet channel before transmitting.
• Nominal Frequency: 13 MHz
• Operating Mode: Fundamental Mode
• Resonance Mode: Parallel Resonant
• Frequency Stability: ±30 ppm
• Series Resistance: <100 ohms
• Load Capacitance: 10 pF
• Drive Level: 10 µW–100 µW
Clocking and Power Management
Receive Signal Strength Indicator (RSSI)
clear the Carrier Detect Register (Reg 0x2F, bit 7=0) and turn
the receiver OFF. Measuring the noise floor of a quiet channel
is inherently a 'noisy' process so, for best results, this
procedure should be repeated several times (~20) to compute
an average noise floor level. A RSSI register value of 0-10
indicates a channel that is relatively quiet. A RSSI register
value greater than 10 indicates the channel is probably being
used. A RSSI register value greater than 28 indicates the
presence of a strong signal.
5.0
5.1
The CYWUSB6935 has a four-wire SPI communication
interface between an application MCU and one or more slave
devices. The SPI interface supports single-byte and multi-byte
serial transfers. The four-wire SPI communications interface
consists of Master Out-Slave In (MOSI), Master In-Slave Out
(MISO), Serial Clock (SCK), and Slave Select (SS).
The SPI receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI
pin. Data to the application MCU is shifted out on the MISO
pin. The active-low Slave Select (SS) pin must be asserted to
initiate a SPI transfer.
The application MCU can initiate a SPI data transfer via a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes as shown in
Figure 5-1 through Figure 5-4. The SS signal should not be
deasserted between bytes. The SPI communications interface
is as follows:
The SPI communications interface has a burst mechanism,
where the command byte can be followed by as many data
bytes as desired. A burst transaction is terminated by
deasserting the slave select (SS = 1). For burst read transac-
tions, the application MCU must abide by the timing shown in
Figure 12-2.
The SPI communications interface single read and burst read
sequences are shown in Figure 5-2 and Figure 5-3, respec-
tively.
The SPI communications interface single write and burst write
sequences are shown in Figure 5-4 and Figure 5-5, respec-
tively.
• Command Direction (bit 7) = “0” Enables SPI read transac-
• Command Increment (bit 6) = “1” Enables SPI auto address
• Six bits of address.
• Eight bits of data.
tion. A “1” enables SPI write transactions.
increment. When set, the address field automatically incre-
ments at the end of each data byte in a burst access, oth-
erwise the same address is accessed.
SPI Interface
Application Interfaces
CYWUSB6935
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