PI7C9X110 Pericom Semiconductor Corporation, PI7C9X110 Datasheet
PI7C9X110
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PI7C9X110 Summary of contents
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... PI7C9X110 PCI Express-to-PCI Reversible Bridge Revision 2.6 ST 3545 North 1 Street, San Jose, CA 95134 Phone: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 Internet: http://www.pericom.com ...
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... The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. Pericom Semiconductor PCIe-to-PCI Reversible Bridge Page 2 of 145 May 2008, Revision 2.6 PI7C9X110 ...
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... The datasheet of PI7C9X110 will be enhanced periodically when updated information is available. The technical information in this datasheet is subject to change without notice. This document describes the functionalities of PI7C9X110 (PCI Express Bridge) and provides technical information for designers to design their hardware using PI7C9X110. Pericom Semiconductor ...
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... PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 36 7.4.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 36 7.4.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 36 7.4.14 SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 36 Pericom Semiconductor PCIe-to-PCI Reversible Bridge Page 4 of 145 May 2008, Revision 2.6 PI7C9X110 ...
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... SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h................................. 56 7.4.62 CAPABILITY ID REGISTER – OFFSET A8h....................................................................................... 57 7.4.63 NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 57 7.4.64 RESERVED REGISTER – OFFSET A8h .............................................................................................. 57 7.4.65 SUBSYSTEM VENDOR ID REGISTER – OFFSET ACh...................................................................... 58 7.4.66 SUBSYSTEM ID REGISTER – OFFSET ACh ...................................................................................... 58 Pericom Semiconductor PCIe-to-PCI Reversible Bridge Page 5 of 145 May 2008, Revision 2.6 PI7C9X110 ...
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... NEXT CAPABILITY OFFSET REGISTER – OFFSET 150h ................................................................ 72 7.4.116 PORT VC CAPABILITY REGISTER 1 – OFFSET 154h ...................................................................... 72 7.4.117 PORT VC CAPABILITY REGISTER 2 – OFFSET 158h ...................................................................... 72 7.4.118 PORT VC CONTROL REGISTER – OFFSET 15Ch............................................................................. 72 Pericom Semiconductor PCIe-to-PCI Reversible Bridge Page 6 of 145 May 2008, Revision 2.6 PI7C9X110 ...
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... UPSTREAM MEMORY 3 BASE ADDRESS REGISTER – OFFSET 60h ............................................. 91 7.5.40 UPSTREAM MEMORY 3 UPPER BASE ADDRESS REGISTER – OFFSET 64h................................ 93 7.5.41 EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h.................................................... 93 7.5.42 MEMORY ADDRESS FORWARDING CONTROL REGISTER – OFFSET 68h .................................. 94 Pericom Semiconductor PCIe-to-PCI Reversible Bridge Page 7 of 145 May 2008, Revision 2.6 PI7C9X110 ...
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... VPD REGISTER – OFFSET D8h ....................................................................................................... 113 7.5.92 VPD DATA REGISTER – OFFSET DCh............................................................................................ 113 7.5.93 UPSTREAM MEMORY 0 TRANSLATED BASE REGISTER – OFFSET E0h .................................... 113 7.5.94 UPSTREAM MEMORY 0 SETUP REGISTER – OFFSET E4h .......................................................... 114 Pericom Semiconductor PCIe-to-PCI Reversible Bridge Page 8 of 145 May 2008, Revision 2.6 PI7C9X110 ...
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... DOWNSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 018h ........................ 125 7.6.7 RESERVED REGISTERS – OFFSET 01Ch TO 030h ......................................................................... 125 7.6.8 UPSTREAM MEMORY 3 SETUP REGISTER – OFFSET 34h........................................................... 125 7.6.9 UPSTREAM MEMORY 3 UPPER 32-BIT SETUP REGISTER – OFFSET 038h............................... 126 Pericom Semiconductor PCIe-to-PCI Reversible Bridge Page 9 of 145 May 2008, Revision 2.6 PI7C9X110 ...
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... IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ....................................................... 136 14.1 INSTRUCTION REGISTER ............................................................................................................................ 136 14.2 BYPASS REGISTER........................................................................................................................................ 136 14.3 DEVICE ID REGISTER ................................................................................................................................... 136 14.4 BOUNDARY SCAN REGISTER ..................................................................................................................... 137 14.5 JTAG BOUNDARY SCAN REGISTER ORDER ............................................................................................ 137 15 POWER MANAGEMENT .................................................................................................... 140 16 ELECTRICAL AND TIMING SPECIFICATIONS........................................................... 141 Pericom Semiconductor Page 10 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... ABSOLUTE MAXIMUM RATINGS............................................................................................................... 141 16.2 DC SPECIFICATIONS..................................................................................................................................... 141 16.3 AC SPECIFICATIONS..................................................................................................................................... 142 17 PACKAGE INFORMATION................................................................................................ 143 18 ORDERING INFORMATION.............................................................................................. 144 Pericom Semiconductor Page 11 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... TABLE OF FIGURES F 1-1 PI7C9X110 T ....................................................................................................................................... 14 IGURE OPOLOGY F 3-1 PCI / PCI-X S ....................................................................................................................................... 21 IGURE ELECTION F 4 IGURE ORWARD AND ON TRANSPARENT F 4 IGURE EVERSE AND RANSPARENT F 16-1 PCI IGURE SIGNAL TIMING CONDITIONS F 17-1 T ......................................................................................................................................... 143 IGURE OP VIEW DRAWING F 17-2 B IGURE OTTOM VIEW DRAWING F 17-3 P IGURE ACKAGE OUTLINE DRAWING ...
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... This page intentionally left blank. Pericom Semiconductor Page 13 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Specification, Revision 3.0 and PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X110 supports transparent and non-transparent mode of operations. Also, PI7C9X110B supports forward and reverse bridging. In forward bridge mode, PI7C9X110 has an x1 PCI Express upstream port and a 32-bit PCI/PCI-X downstream port. The 32-bit PCI downstream port is 66MHz capable (see figure 1-1). In reverse bridge mode, PI7C9X110 has a 32-bit PCI upstream port and an x1 PCI Express downstream port ...
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... EEPROM (I2C) Interface • SM Bus Interface • Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support • Power consumption at about 1.0 Watt in typical condition • Extended commercial/industrial temperature range (-40C to 85C) Pericom Semiconductor Page 15 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... PAR one clock after the address phase and tri-state PAR during data phases. PAR is tri-stated one cycle after the AD lines are tri-stated. During bus idle, PI7C9X110B drives PAR to a valid logic level when arbiter is parking to PI7C9X110B on PCI bus. B FRAME (Active LOW): Driven by the initiator of a transaction to indicate the beginning and duration an access ...
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... Request (Active LOW): REQ_L’s are asserted by bus master devices to request for transactions on the PCI bus. The master devices de-assert REQ_Ls for at least 2 PCI clock cycles before asserting them again. If external arbiter is selected (CFN_L=1), REQ_L [0] will be the bus grant input to PI7C9X110. Also, REQ_L [5:2] will become the GPI [3:0]. O Grant (Active LOW): PI7C9X110 asserts GNT_Ls to release PCI bus control to bus master devices ...
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... TM0 is also a strapping pin. See table 3-1 for mode selection and 3-2 for strapping control. I Mask Input for CLKOUT: MSK_IN is used by PI7C9X110 to enable or disable the clock outputs. MSK_IN is also a strapping pin. When it is strapped to high, hot-plug is enabled. See table 3-2 for strapping control. ...
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... Pericom Semiconductor TYPE DESCRIPTION I PCI-X Capability Pin: PI7C9X110 can be forced to PCI mode if PCIXCAP is tied to ground with a capacitor (0.1uF) in parallel. If PCIXCAP is connected to ground through a capacitor (0.1uF), PI7C9X110 will be in 133MHz PCI-X mode. If PCIXCAP is connected to ground through a resistor (10K Ohm) with a capacitor (0.1uF) in parallel, PI7C9X110 will be in 66MHz PCI-X mode. ...
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... FUNCTIONAL MODE SELECTION If TM2 is strapped to low, PI7C9X110 uses TM1, TM0, CFN_L, and REVRSB pins to select different modes of operations. These four input signals are required to be stable during normal operation. One of the sixteen combinations of normal operation can be selected by setting the logic values for the four mode select pins. For example, if the logic values are low for all four (TM1, TM0, CFN_L, and REVRSB) pins, the normal operation will have EEPROM (I2C) support in transparent mode with internal arbiter in forward bridge mode ...
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... If PI7C9X110 sees a logic LOW on PCIXCAP, one or more devices on the secondary have either pulled the signal to ground (PCI-X 66MHz capable) or tied it to ground (only capable of conventional PCI mode). To differentiate between the two conditions, PI7C9X110 then enables PCIXUP to put the strong pull-up into the circuit node. If PCIXCAP remains at logic LOW, it must be tied to ground by one or more devices, and the bus is initialized to conventional PCI mode ...
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... PCI based systems and peripherals are ubiquitous in the I/O interconnect technology market today. It will be a tremendous effort to convert existing PCI based products to be used in PCI Express systems. PI7C9X110 provides a solution to bridge existing PCI based products to the latest PCI Express technology. Figure 4-1 Forward and Non-transparent Bridge Mode ...
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... Express bridge that its PCI bus interface is connected to the host chipset between and the PCI Express x1 link. It enables the legacy PCI Host Systems to provide PCI Express capability. PI7C9X110 provides a solution to convert existing PCI based designs to adapt quickly into PCI Express base platforms. Existing PCI based applications will not have to undergo a complete re-architecture in order to interface to PCI Express technology ...
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... TRANSPARENT AND NON-TRANSPARENT BRIDGING 5.1 TRANSPARENT MODE In transparent bridge mode, base class code of PI7C9X110 is set to be 06h (bridge device). The sub-class code is set to be 04h (PCI-to-PCI bridge). Programming interface is 00h. Hence, PI7C9X110 is not a subtractive decoding bridge. PI7C9X110 has type-1 configuration header if TM0 is set to 0 (transparent bridge mode). These configuration registers are the same as traditional transparent PCI-to-PCI Bridge ...
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... Lower 4K I/O or Memory access offset 054h Lower 4K I/O or Memory access offset 100h to 1FFh Configuration access offset 63h Configuration access offset 67h Lower 4K I/O or Memory access offset 34h Lower 4K I/O or Memory access offset 38h Page 25 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... TLP STRUCTURE PCI Express TLP (Transaction Layer Packet) Structure is comprised of format, type, traffic class, attributes, TLP digest, TLP poison, and length of data payload. There are four TLP formats defined in PI7C9X110 based on the states of FMT [1] and FMT [0] as shown on Table 6-1. Table 6-1 TLP Format ...
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... When pin TM0=0, PI7C9X110 will be in transparent bridge mode and the configuration registers for transparent bridge should be used. When pin TM0=1, PI7C9X110 will be in non-transparent bridge mode and the configuration registers for non- transparent bridge should be used. 7.1 CONFIGURATION REGISTER MAP PI7C9X110 supports capability pointer with PCI-X (ID=07h), PCI power management (ID=01h), PCI bridge sub- system vendor ID (ID=0Dh), PCI Express (ID=10h), vital product data (ID=03h), and message signaled interrupt (ID=05h) ...
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... Upper 32-bit BAR PCI Express Tx and Rx PCI Express Tx and Rx Control Control Reserved Memory Address Forwarding Control Reserved Reserved Reserved Subsystem Vendor ID Reserved Subsystem ID Page 28 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge EEPROM SM Bus (I2C) Access Access No Yes No Yes Yes2 Yes5 Yes2 Yes5 ...
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... XPIP Configuration Register 1 Register 1 XPIP Configuration XPIP Configuration Register 2 Register 2 Reserved Reserved VPD Capability VPD Capability Register Register VPD Data Register VPD Data Register Page 29 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge EEPROM SM Bus (I2C) Access Access No Yes No Yes No Yes ...
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... PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP PI7C9X110 also supports PCI Express Extended Capabilities with from 257-byte to 4096-byte space. The offset range is from 100h to FFFh. The offset 100h is defined for Advance Error Reporting (ID=0001h). The offset 150h is defined for Virtual Channel (ID=0002h). ...
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... XXXX_XXXXh 2 Translated Base Downstream Memory 0000_0000h 2 Setup Downstream Memory XXXX_XXXXh 3 Translated Base Downstream Memory 0000_0000h 3 Setup Downstream Memory 0000_0000h 3 Upper 32-bit Setup Reserved 0 Page 31 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge EEPROM SM Bus (I2C) Access Access No Yes No Yes No Yes No Yes No Yes ...
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... Scratch pad 6 XXXX_XXXXh Scratch pad 7 XXXX_XXXXh Reserved 0 Upstream Memory 2 0 Lookup Table Reserved 0 Descriptions Read Only Read Only and Sticky Read/Write Page 32 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge EEPROM SM Bus (I2C) Access Access No Yes Yes Yes Yes Yes No Yes No Yes ...
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... PCI-X mode, the bridge is allowed to initiate a split completion transaction regardless of the status bit. Reset PI7C9X110 does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset PI7C9X110 does not originate a Memory Write and Invalidate transaction ...
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... Reset to 00000 TYPE DESCRIPTION RO Reset to 000 RO Reset PI7C9X110 supports the capability list (offset 34h in the pointer to the data structure) Reset This bit applies to reverse bridge only. 1: 66MHz capable Reset to 0 when forward bridge or 1 when reverse bridge. RO Reset This bit applies to reverse bridge only ...
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... DESCRIPTION This bit is set when PI7C9X110 receives a completion with completer abort completion status on the primary REVERSE BRIDGE – This bit is set when PI7C9X110 detects a target abort on the primary Reset to 0 RWC FORWARD BRIDGE – This bit is set when PI7C9X110 receives a completion with unsupported request completion status on the primary REVERSE BRIDGE – ...
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... Reset to 00h TYPE DESCRIPTION RW Reset to 00h TYPE DESCRIPTION RW / Secondary latency timer in PCI / PCI-X mode RO FORWARD BRIDGE – RW with reset to 00h in PCI mode or 40h in PCI-X mode REVERSE BRIDGE – RO with reset to 00h Page 36 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset to 01 when forward mode or 00 when reverse mode. RWC FORWARD BRIDGE – Bit is set when PI7C9X110 signals target abort REVERSE BRIDGE – Bit is set when PI7C9X110 completes a request using completer abort completion status Reset to 0 Page 37 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... Bit is set when PI7C9X110 receives a completion with completer abort completion status on the secondary interface Reset to 0 RWC FORWARD BRIDGE – Bit is set when PI7C9X110 detects master abort on the secondary interface REVERSE BRIDGE – Bit is set when PI7C9X110 receives a completion with unsupported request completion status on the primary interface Reset to 0 RWC FORWARD BRIDGE – ...
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... BIT FUNCTION 19:16 64-bit Addressing Support 31:20 Prefetchable Memory Limit Pericom Semiconductor TYPE DESCRIPTION RO 0001: Indicates PI7C9X110 supports 64-bit addressing Reset to 0001 RW Prefetchable Memory Limit (00000000_000FFFFFh) Reset to 000h Page 39 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Expansion ROM not supported. Reset to 00000000h TYPE DESCRIPTION RW These bits apply to reverse bridge only. For initialization code to program to tell which input of the interrupt controller the PI7C9X110’s INTA_L in connected to. Reset to 00000000 Page 40 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... PCIe link for reverse bridge 1: Force the assertion of RESET_L on secondary PCI bus for forward bridge, or generate a hot reset on the PCIe link for reverse bridge Reset Fast back-to-back not supported Reset to 0 Page 41 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Full prefetch if address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after the read multiple is terminated either by an external master or by the PI7C9X110, until the discard time expires Reset to 10 ...
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... Retry any master at PCI bus that repeats its transaction with command code changes. 1: Allows any master at PCI bus to change memory command code (MR, MRL, MRM) after it has received a retry. The PI7C9X110 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. ...
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... Reset PI7C9X110 configuration space can be accessed from both interfaces RW 1: PI7C9X110 configuration space can only be accessed from the secondary interface. Primary bus accessed receives completion with CRS status for forward bridge, or target retry for reverse bridge Reset TM0 is LOW ...
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... Pericom Semiconductor Page 45 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Enable Pericom Semiconductor TYPE DESCRIPTION RO Reset to 00000000h TYPE DESCRIPTION RW 0: Disable arbitration for internal PI7C9X110 request 1: Enable arbitration for internal PI7C9X110 request Reset Disable arbitration for master 1 1: Enable arbitration for master 1 Reset Disable arbitration for master 2 ...
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... GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting FRAME_L Reset Reset to 0 TYPE DESCRIPTION RW 0: Low priority request to internal PI7C9X110 1: High priority request to internal PI7C9X110 Reset Low priority request to master 1 1: High priority request to master 1 Reset ...
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... Reset to 0000 RW 0000: 0.00 db 0001: -0.35 db 0010: -0.72 db 0011: -1.11 db 0100: -1.51 db 0101: -1.94 db 0110: -2.38 db 0111: -2.85 db 1000: -3.35 db 1001: -3.88 db 1010: -4.44 db 1011: -5.04 db 1100: -5.68 db 1101: -6.38 db 1110: -7.13 db 1111: -7.96 db Reset to 1000 RW 00: 52 ohms 01: 57 ohms 10: 43 ohms 11: 46 ohms Reset to 00 Page 48 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... PCLK / 4096 01: PCLK / 2048 10: PCLK / 1024 11: PCLK / 128 Reset Enable EEPROM autoload 1: Disable EEPROM autoload Reset Normal speed of EEPROM autoload 1: Increase EEPROM autoload by 32x Reset to 0 Page 49 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... TYPE DESCRIPTION RO 0: EEPROM autoload is not on going 1: EEPROM autoload is on going Reset EEPROM word address for EEPROM cycle Reset to 0000000 RW EEPROM data to be written into the EEPROM Reset to 0000h Page 50 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... RO / This bit is a read-only and set reverse bridge mode or is read-write in RWC forward bridge mode When this is set split completion has been discarded by PI7C9X110 at secondary bus because the requester did not accept the split completion transaction Reset to 0 RWC ...
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... Reset to 0 RWC When this bit is set split request is delayed because PI7C9X110 is not able to forward the split request transaction to its secondary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register ...
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... Reset to 0 RWC When this bit is set split request is delayed because PI7C9X110 is not able to forward the split request transaction to its primary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register ...
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... ADQs. This field can be programmed to any value or equal to the content of the split capability field. For example, if the limit is set to FFFFh, PI7C9X110 is allowed to forward all split requests of any size regardless of the amount of buffer space available. The split transaction commitment limit is set to 0010h that is the same value as the split transaction capability ...
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... TYPE DESCRIPTION RW Power State is used to determine the current power state of PI7C9X110 non-implemented state is written to this register, PI7C9X110 will ignore the write data. When present state is D3 and changing to D0 state by programming this register, the power state change causes a device reset ...
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... S_CLKOUT3 01: enable S_CLKOUT3 10: enable S_CLKOUT3 11: disable S_CLKOUT3 and driven LOW Reset S_CLKOUT (Device 1) Enable for forward bridge mode only 0: enable S_CLKOUT4 1: disable S_CLKOUT4 and driven LOW Reset to 0 Page 56 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Capability ID for subsystem ID and subsystem vendor ID Reset to 0Dh TYPE DESCRIPTION RO Next item pointer (point to PCI Express Capability by default but can be programmed to A0h if Slot Identification Capability is enabled) Reset to B0h TYPE DESCRIPTION RO Reset to 0000h Page 57 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset Reset to 0 TYPE DESCRIPTION RO 000: 128 bytes 001: 256 bytes 010: 512 bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset to 001 Page 58 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... RO Reset to 000 RO These bits are set by the Set_Slot_Power_Limit message Reset to 00h RO This value is set by the Set_Slot_Power_Limit message Reset Reset to 0h TYPE DESCRIPTION RW Reset Reset Reset to 0h Page 59 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... TYPE DESCRIPTION RW Reset Relaxed Ordering disabled Reset This field sets the maximum TLP payload size for the PI7C9X110 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved ...
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... Reset Reset Read completion boundary not supported Reset for Forward Bridge RW Reset for Forward Bridge RW Reset Reset Reset Reset to 00h TYPE DESCRIPTION Page 61 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. RO Reset to 00h RO Reset Reset Reset to 0 TYPE DESCRIPTION RW Reset Reset to 0 Page 62 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset Reset to 0 TYPE DESCRIPTION RW Reset to 54h A Fast Training Sequence order set composes of one K28.5 (COM) Symbol and three K28.1 Symbols. RW Reset Reset Reset to 19h RO Reset to 0 Page 63 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Pericom Semiconductor Page 64 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... The least significant byte of this register corresponds to the byte of VPD at the address specified by the VPD address register. The data read form or written to this register uses the normal PCI byte transfer capabilities. Reset to 0 Page 65 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset to 000 RW Reset Reset to 00h TYPE DESCRIPTION RO Reset Reset to 0 TYPE DESCRIPTION RW Reset to 0 Page 66 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset Reset to 0 TYPE DESCRIPTION RWS Reset Reset to 0 RWS Reset Reset to 0 RWS Reset to 0 RWS Reset to 0 Page 67 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset to 0 RWCS Reset Reset to 0 TYPE DESCRIPTION RWS Reset Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset Reset to 0 RWS Reset Reset to 0 Page 68 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset to 0 ROS Reset to 0 ROS Reset to 0 ROS Reset to 0 TYPE DESCRIPTION RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset Reset to 0 RWCS Reset to 0 Page 69 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... RWS Reset to 1 RWS Reset to 0 RWS Reset to 1 RWS Reset Reset to 0 TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset Reset to 0 Page 70 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... DAC transaction Reset to 0 ROS Reset to 0 ROS Transaction address, AD [31:0] during first address phase Reset to 0 ROS Transaction address, AD [31:0] during second address phase of DAC transaction Reset to 0 TYPE DESCRIPTION RO Reset to 0002h Page 71 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset Reset Reset to 0 TYPE DESCRIPTION RO Reset Reset to 0 TYPE DESCRIPTION RO Reset Reset Reset Reset to0 RO Reset Reset Reset to 0 TYPE DESCRIPTION Page 72 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... Reset Reset to 0 TYPE DESCRIPTION RW Replay Timer Reset Replay Timer Enable Reset Reset Acknowledge Latency Timer Reset Acknowledge Latency Timer Enable Reset Reset to 0 Page 73 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... PCI-X mode, the bridge is allowed to initiate a split completion transaction regardless of the status bit. Reset PI7C9X110 does not respond as a target to Special Cycle transactions, so this bit is defined as Read-Only and must return 0 when read Reset PI7C9X110 does not originate a Memory Write and Invalidate transaction ...
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... Reset to 000 INTx interrupt message request pending in PI7C9X110 primary 1: INTx interrupt message request pending in PI7C9X110 primary Reset PI7C9X110 supports the capability list (offset 34h in the pointer to the data structure) Reset This bit applies to reverse bridge only. 1: 66MHz capable Reset to 0 when forward bridge or 1 when reverse bridge ...
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... FORWARD BRIDGE – This bit is set when bridge receives a completion with completer abort completion status on the primary REVERSE BRIDGE – This bit is set when PI7C9X110 detects a target abort on the primary Reset to 0 RWC FORWARD BRIDGE – This bit is set when PI7C9X110 receives a completion with unsupported request completion status on the primary REVERSE BRIDGE – ...
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... REVERSE BRIDGE – RW with reset to 00h in PCI mode or 40h in PCI-X mode TYPE DESCRIPTION RO Type-0 header format configuration (10-3Fh) Reset to 0000000 (non-transparent mode Indicates single function device Reset Reset to 00h TYPE DESCRIPTION RO 0: Memory space 1: IO space Page 77 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
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... EEPROM (I2C Bus or Local Processor. The range of this register is from 4KB to 2GB. The lower 4KB if this address reange map to the PI7C9X110 CSRs into memory space. The remaining space is this range above 4KB, if any, specifies a range for forwarding downstream memory transactions. PI7X9X110 uses downstream Memory 0 Translated Base Register (Offset 98h) to formulate direct address translation ...
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... Offset 014h and 018h) to disable this register. The range of this register is from 4KB to 9EB for memory space. PI7C9X110 uses Memory 3 Translated Base Register (CSR Offset 010h) to formulate direct address translation when 32-bit addressing programmed. When 64-bit addressing programmed, no address translation is performed bit in the setup register is set to one, then the correspondent bit of this register will be changed to RW ...
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... Expansion ROM not supported. Reset to 00000000h TYPE DESCRIPTION RW These bits apply to reverse bridge only. For initialization code to program to tell which input of the interrupt controller the PI7C9X110’s INTA_L in connected to. Reset to 00000000 TYPE DESCRIPTION Page 80 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... Reset to 00h when forward mode or 01h when reverse mode. TYPE DESCRIPTION RO This register is valid only in reverse bridge mode. It specifies how long of a burst period that PI7C9X110 needs on the primary bus in the units of ¼ microseconds. Reset to 0 Page 81 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
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... Full prefetch if memory read line address is in prefetchable range at PCI interface 11: Full prefetch if address is in prefetchable range at PCI interface and the PI7C9X110 will keep remaining data after the read line is terminated either by an external master or by the PI7C9X110, until the discard timer expires Reset to 00 Page 82 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2 ...
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... Retry any master at PCI bus that repeats its transaction with command code changes. 1: Allows any master at PCI bus to change memory command code (MR, MRL, MRM) after it has received a retry. The PI7C9X110 will complete the memory read transaction and return data back to the master if the address and byte enables are the same. ...
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... Reset PI7C9X110 configuration space can be accessed from both interfaces RW 1: PI7C9X110 configuration space can only be accessed from the secondary interface. Primary bus accessed receives completion with CRS status for forward bridge, or target retry for reverse bridge Reset TM0 is LOW ...
Page 85
... Reset to 000 INTx interrupt message request pending in PI7C9X110 secondary 1: INTx interrupt message request pending in PI7C9X110 secondary Reset PI7C9X110 supports the capability list (offset 34h in the pointer to the data structure) Reset to 1 Page 85 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
Page 86
... REVERSE BRIDGE – This bit is set when bridge receives a completion with completer abort completion status on the secondary FORWARD BRIDGE – This bit is set when PI7C9X110 detects a target abort on the secondary Reset to 0 RWC REVERSE BRIDGE – This bit is set when PI7C9X110 receives a completion with unsupported request completion status on the secondary FORWARD BRIDGE – ...
Page 87
... This bit is set when address or data parity error is detected on the secondary Reset to 0 TYPE DESCRIPTION RW 0: Disable arbitration for internal PI7C9X110request 1: Enable arbitration for internal PI7C9X110 request Reset Disable arbitration for master 1 1: Enable arbitration for master 1 Reset ...
Page 88
... GNT_L de-asserts for 1 clock after 2 clocks of the granted master asserting FRAME_L Reset Reset to 0 TYPE DESCRIPTION RW 0: Low priority request to internal PI7C9X110 1: High priority request to internal PI7C9X110 Reset Low priority request to master 1 1: High priority request to master 1 Reset ...
Page 89
... RW with reset to 00h in PCI mode or 40h in PCI-X mode TYPE DESCRIPTION RO Type-0 header format configuration (10 – 3Fh) Reset to 0000000 RO 0: Indicates single function device Reset Reset to 00h TYPE DESCRIPTION RO 0: Memory space 1: IO space Reset to 0 Page 89 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 90
... EEPROM (I2C Bus or Local Processor. The range of this register is from 4KB to 2GB. The lower 4KB if this address reange map to the PI7C9X110 CSRs into memory space. The remaining space is this range above 4KB, if any, specifies a range for forwarding upstream memory transactions. PI7X9X110 uses upstream Memory 0 Translated Base Register (Offset E0h) to formulate direct address translation ...
Page 91
... RW/RO This Base Address register defines the address range for upstream memory transactions. PI7C9X110 uses a lookup table to do the address translation. The address range of this register is from 16KB to 2GB in memory space. The address range is divided into 64 pages. The size of each page is defined by Memory Address Forwarding Control register (Offset 6Ah), which is initialized by EEPROM (I2C Bus or local processor ...
Page 92
... EEPROM (I2C Bus or Local Processor. Writing a zero to bit [31] of the setup registers (CSR Offset 034h and 038h) to disable this register. The range of this register is from 4KB to 9EB for memory space. PI7C9X110 uses this register and the Upstream Memory 3 Upper Base Address Register when 64-bit addressing programmed (bit [21] of Offset 68h) ...
Page 93
... Offset 038h) to disable this register. This register defines the upper 32 bits of a memory range for upstream forwarding memory. PI7C9X110 uses this register and the Upstream Memory 3 Base Address Register when 64-bit addressing programmed (bit [21] of Offset 68h). When 64-bit addressing is disabled, no address translation is performed ...
Page 94
... Any 64-bit address transactions on secondary interface falling outside of Downstream Memory 3 address range are forwarded upstream 1: Enable 64-bit address transaction forwarding upstream based on Upstream Memory 3 address range without address translation Reset Reset to 0 Page 94 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 95
... EEPROM autoload is not successfully completed 1: EEPROM autoload is successfully completed Reset Where PCLK is 125MHz 00: PCLK / 4096 01: PCLK / 2048 10: PCLK / 1024 11: PCLK / 128 Reset Enable EEPROM autoload 1: Disable EEPROM autoload Reset to 0 Page 95 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 96
... SERR_L (if enabled). Reset Primary discard timer counts 215 PCI clock cycles 1: Primary discard timer counts 210 PCI clock cycles FORWARD BRIDGE – Bit is RO and ignored by PI7C9X110 Reset to 0 Page 96 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 97
... Reset to 00h when reverse mode or 01h when forward mode. TYPE DESCRIPTION RO This register is valid only in forward bridge mode. It specifies how long of a burst period that PI7C9X110 needs on the secondary bus in the units of ¼ microseconds. Reset to 0 Page 97 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge ...
Page 98
... Reset to 0 RWC When this bit is set split request is delayed because PI7C9X110 is not able to forward the split request transaction to its secondary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register ...
Page 99
... RO / This bit is a read-only and set reverse bridge mode or is read-write in RWC forward bridge mode When this is set split completion has been discarded by PI7C9X110 at primary bus because the requester did not accept the split completion transaction Reset to 0 RWC ...
Page 100
... Reset to 0 RWC When this bit is set split request is delayed because PI7C9X110 is not able to forward the split request transaction to its primary bus due to insufficient room within the limit specified in the split transaction commitment limit field of the downstream split transaction control register ...
Page 101
... TYPE DESCRIPTION RW Power State is used to determine the current power state of PI7C9X110 non-implemented state is written to this register, PI7C9X110 will ignore the write data. When present state is D3 and changing to D0 state by programming this register, the power state change causes a device reset ...
Page 102
... RO 0: Set the corresponding bit in the Base Address Register to read only. (WS) 1: Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. Reset to 7FFFFh Page 102 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 103
... Capability ID Pericom Semiconductor TYPE DESCRIPTION RO Always set to 1 when a bus master attempts to write a zero to this bit. (WS) PI7C9X110 returns bit [31:12] as FFFFFh (for 4KB size). Reset to 1 TYPE DESCRIPTION RO Capability ID for Slot Identification off by default but can be turned on through EEPROM interface Reset to 04h ...
Page 104
... S_CLKOUT2 11: disable S_CLKOUT2 and driven LOW Reset S_CLKOUT (Slot 3) Enable for forward bridge mode only 00: enable S_CLKOUT3 01: enable S_CLKOUT3 10: enable S_CLKOUT3 11: disable S_CLKOUT3 and driven LOW Reset to 00 Page 104 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 105
... Define the translated base address for downstream I/O or memory transactions whose initiator addresses fall into Downstream I/O or Memory 1 address range. The number of bits that are used for translated base is determined by its setup register (offset ACh) Reset to 00000h Page 105 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 106
... PCI Express to PCI bridge 1000: PCI to PCI Express bridge Others: Reserved Reset to 7h for Forward Bridge or 8h for Reverse Bridge RO Reset to 0 for Forward Bridge or 1 for Reverse Bridge RO Reset Reset to 0 Page 106 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 107
... If Hot Plug is disabled 1: If Hot Plug is enable at Forward Bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. RO Reset to 000 RO These bits are set by the Set_Slot_Power_Limit message Reset to 00h Page 107 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 108
... RW Reset Reset Relaxed Ordering disabled Reset This field sets the maximum TLP payload size for the PI7C9X110 000: 128 bytes 001: 256 bytes 010: 512 bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved ...
Page 109
... L0’s and L1’s entry enabled Reset Reset Read completion boundary not supported Reset for Forward Bridge RW Reset for Forward Bridge RW Reset Reset to 0 Page 109 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 110
... BIT FUNCTION 7 Extended Sync 15:8 Reserved Pericom Semiconductor TYPE DESCRIPTION RW Reset Reset to 00h Page 110 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 111
... If Hot Plug is disabled 1: If Hot Plug is enabled at reverse bridge Reset to 0 when hot-plug is disabled or 1 when hot-plug is enabled through strapping. RO Reset to 00h RO Reset Reset Reset to 0 TYPE DESCRIPTION Page 111 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 112
... Reset to 0400h TYPE DESCRIPTION RW Reset Reset Reset to 0 TYPE DESCRIPTION RW Reset to 54h A Fast Training Sequence order set composes of one K28.5 (COM) Symbol and three K28.1 Symbols. RW Reset to 2h Page 112 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 113
... Define the translated base address for upstream memory transactions whose initiator addresses fall into Upstream Memory 0 (above lower 4K boundary) address range. The number of bits that are used for translated base is determined by its setup register (offset E4h) Reset to 00000h Page 113 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 114
... Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range. Reset to 00000h RO Always set to 1 when a bus master attempts to write a zero to this bit. (WS) PI7C9X110 returns bit [31:12] as FFFFFh (for 4KB size). Reset to 1 TYPE DESCRIPTION RO Reset to 000000 ...
Page 115
... BIT FUNCTION 31 Base Address Register Enable Pericom Semiconductor TYPE DESCRIPTION RO 0: Disable this Base Address Register (WS) 1: Enable this Base Address Register Reset to 0 Page 115 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 116
... Reset to 000 RW Reset Reset to 00h TYPE DESCRIPTION RO Reset Reset to 0 TYPE DESCRIPTION RW Reset to 0 TYPE DESCRIPTION Page 116 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 117
... Reset to 0 RWCS Reset Reset to 0 TYPE DESCRIPTION RWS Reset Reset to 0 RWS Reset Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 Page 117 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 118
... Reset to 0 RWCS Reset Reset to 0 TYPE DESCRIPTION RWS Reset Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset Reset to 0 RWS Reset Reset to 0 Page 118 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 119
... Reset to 0 ROS Reset to 0 ROS Reset to 0 ROS Reset to 0 TYPE DESCRIPTION RWCS Reset to 0 RWCS Reset to 0 RWCS Reset to 0 RWCS Reset Reset to 0 RWCS Reset to 0 Page 119 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 120
... RWS Reset to 1 RWS Reset to 0 RWS Reset to 1 RWS Reset Reset to 0 TYPE DESCRIPTION RWS Reset to 0 RWS Reset to 0 RWS Reset to 0 RWS Reset Reset to 0 Page 120 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 121
... DAC transaction Reset to 0 ROS Reset to 0 ROS Transaction address, AD [31:0] during first address phase Reset to 0 ROS Transaction address, AD [31:0] during second address phase of DAC transaction Reset to 0 TYPE DESCRIPTION RO Reset to 0002h Page 121 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 122
... Reset Reset Reset to 0 TYPE DESCRIPTION RO Reset Reset to 0 TYPE DESCRIPTION RO Reset Reset Reset Reset to0 RO Reset Reset Reset to 0 TYPE DESCRIPTION Page 122 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 123
... Reset Reset to 0 TYPE DESCRIPTION RW Replay Timer Reset Replay Timer Enable Reset Reset Acknowledge Latency Timer Reset Acknowledge Latency Timer Enable Reset Reset to 0 Page 123 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 124
... Set the corresponding bit in the Base Address Register to read/write in order to control the size of the address range Reset to 00000h RO 0: Disable this Base Address Register (WS) 1: Enable this Base Address Register Reset to 0 TYPE DESCRIPTION RO Reset to 000000 Page 124 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 125
... RW) 0: Disable 64-bit Base Address Register 1: Enable 64-bit Base Address Register Reset to 0 TYPE DESCRIPTION RO 0: Memory space is requested Reset 00: 32-bit address space 01: 64-bit address space Reset to 01 Page 125 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 126
... Lookup Table Data access. Reset to 00h RO Reset to 0 TYPE DESCRIPTION RW 0: Invalid lookup 1: Valid lookup Reset Reset Memory address is non-prefetchable 1: Memory address is Reset Reset to 0h Page 126 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 127
... PI7C9X110 initiates an interrupt request on secondary interface when the interrupt request bit is set and the corresponding Upstream Page Boundary IRQ 1 Mask bit is reset. When forward bridge, PI7C9X110 asserts INTA_L or generates MSI on secondary bus (PCI interface). When reverse bridge, PI7C9X110 sends INTA_L assertion message or generates MSI on secondary interface (PCI Express). When wrting a “ ...
Page 128
... Reset to FFFFFFFFh TYPE DESCRIPTION RWC 0: PI7C9X110 can initiate an interrupt request when the correspondent request bit is set 1: PI7C9X110 cannot initiate any interrupt request even though the correspondent request bit is set Reset to FFFFFFFFh TYPE DESCRIPTION RWC When writing “1” to this register bit, it clears the correspondent interrupt request bit ...
Page 129
... When reading this register, it returns the Secondary Clear IRQ Mask bit status allows to clear an interrupt request on secondary interface 1: It does not allow to clear any interrupt request on secondary interface Reset to FFFFh Page 129 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 130
... The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h Page 130 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 131
... The external devices can use the scratchpad as a temporary storage. Primary and secondary bus devices can communicate through the scratchpad. However, writing and reading the scratchpad does not generate any interrupt request. Reset to 00000000h Page 131 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 132
... Reset to unknown Page 132 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge rd 63 page: bit [2015:1984 page: bit [1951:1920 page: bit [1887:1856 page: bit [1823:1792] ...
Page 133
... Address bit [1] GPIO [3:0] pins can be further defined to serve other functions in the next generation Device. Four GPI [3:0] and four GPO [3:0] have been added to PI7C9X110 when external arbiter is selected (CFN_L=1). If external arbiter is selected, REQ_L [5:2] and GNT [5:2] will become the GPI [3:0] and GPO [3:0] respectively. ...
Page 134
... In reverse bridge mode, PI7C9X110 maps the interrupt message packets to PCI interrupt pins or MSI if MSI is enable (see configuration register bit [16] of Offset F0h). In forward bridge mode, PI7C9X110 maps the PCI interrupts pins or MSI if enable on PCI side to interrupt message packets on PCIe side. There are eight interrupt message packets. They are Assert_INTA, Assert_INTB, Assert_INTC, Assert_INTD, Deassert_INTA, Deassert_INTB, Deassert_INTC, and Deassert_INTD ...
Page 135
... A warm reset is a reset that triggered by the hardware without removing and re-applying the power sources to PI7C9X110. • Hot Reset: A hot reset is a reset that used an in-band mechanism for propagating reset across a PCIe link to PI7C9X110. PI7C9X110 will enter to training control reset when it receives two consecutive TS1 or TS2 order-sets with reset bit set. • ...
Page 136
... Symbol Times. PI7C9X110 does not keep PCI/PCI-X reset active when VD33 power is off even though VAUX (3.3v) is supported recommended to add a weak pull-down resistor on its application board to ensure PCI/PCI-X reset is low when VD33 power is off (see section 7.3.2 of PCI Bus Power management Specification Revision 1 ...
Page 137
... The boundary scan register has a set of serial shift-register cells. A chain of boundary scan cells is formed by connected the internal signal of the PI7C9X110 package pins. The VDD, VSS, and JTAG pins are not in the boundary scan chain. The input to the shift register is TDI and the output from the shift register is TDO. There are 4 different types of boundary scan cells, based on the function of each signal pin ...
Page 138
... A7 BIDIR - CONTROL C6 BIDIR - CONTROL B6 BIDIR - CONTROL D5 BIDIR - CONTROL C5 BIDIR - CONTROL A5 BIDIR - CONTROL D4 BIDIR - CONTROL B4 BIDIR - CONTROL A4 BIDIR - CONTROL B3 BIDIR - CONTROL Page 138 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge Tri-state Control Cell - ...
Page 139
... CONTROL L8 BIDIR - CONTROL P9 OUTPUT3 N9 OUTPUT3 L9 OUTPUT3 P10 OUTPUT3 M10 OUTPUT3 L10 OUTPUT3 N11 OUTPUT3 P12 OUTPUT3 N12 OUTPUT3 - CONTROL P13 BIDIR - CONTROL Page 139 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge Tri-state Control Cell 100 - 102 - - - - - - - - - 112 - 114 - 122 122 ...
Page 140
... VDDAUX, VDDCAUX, and VAUX with the auxiliary power supplies to maintain all necessary information to be restored to the full power D0 state. PI7C9X110 has been designed to have sticky registers that are powered by auxiliary power supplies. PME_L pin allows PCI devices to request power management state changes. ...
Page 141
... In order to support auxiliary power management fully recommended to have VDDP and VDDAUX separated. By the same token, VD33/VDDC and VAUX/VDDCAUX need to be separated for auxiliary power management support. However, if auxiliary power management is not required, VD33 and VDDC can be connected to VAUX and VDDCAUX respectively. The typical power consumption of PI7C9X110 is about 1.0 watt. Pericom Semiconductor o -65 ...
Page 142
... PI7C9X110 is capable of sustaining 1500V human body model for the ESD protection without any damages. 16.3 AC SPECIFICATIONS Table 16-3 PCI bus timing parameters Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu (ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to signal valid delay – ...
Page 143
... PACKAGE INFORMATION Figure 17-1 Top view drawing Figure 17-2 Bottom view drawing Pericom Semiconductor Page 143 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...
Page 144
... The package of PI7C9X110 is a 12mm x 12mm LFBGA (160 Pin) package. The ball pitch is 0.8mm and the ball size is 0.5mm. The following are the package information and mechanical dimension: Figure 17-3 Package outline drawing 18 ORDERING INFORMATION PART NUMBER PIN – PACKAGE PI7C9X110BNBE 160 – LFBGA PI7C9X110BNB 160 – ...
Page 145
... NOTES: Pericom Semiconductor Page 145 of 145 PI7C9X110 PCIe-to-PCI Reversible Bridge May 2008, Revision 2.6 ...