IS61C256AL Integrated Silicon Solution, Inc., IS61C256AL Datasheet

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IS61C256AL

Manufacturer Part Number
IS61C256AL
Description
32k X 8 High-speed Cmos Static Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet

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FUNCTIONAL BLOCK DIAGRAM
IS61C256AL
32K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 10, 12 ns
• CMOS Low Power Operation
• Fully static operation: no clock or refresh
• TTL compatible inputs and outputs
• Single 5V power supply
• Lead-free available
Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
10/23/06
— 1 mW (typical) CMOS standby
— 125 mW (typical) operating
required
I/O0-I/O7
A0-A14
GND
VDD
WE
OE
CE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
1-800-379-4774
DESCRIPTION
The
32,768 word by 8-bit static RAMs. It is fabricated using
ISSI
reliable process coupled with innovative circuit design
techniques, yields access times as fast as 10 ns maximum.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 150 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active
LOW Chip Enable (CE) input and an active LOW Output
Enable (OE) input. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IS61C256AL is pin compatible with other 32Kx8 SRAMs
and are available in 28-pin SOJ and TSOP (Type I)
packages.
ISSI
's high-performance CMOS technology. This highly
MEMORY ARRAY
IS61C256AL is a very high-speed, low power,
COLUMN I/O
32K X 8
OCTOBER 2006
ISSI
®
1

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IS61C256AL Summary of contents

Page 1

... Easy memory expansion is provided by using an active LOW Chip Enable (CE) input and an active LOW Output Enable (OE) input. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61C256AL is pin compatible with other 32Kx8 SRAMs and are available in 28-pin SOJ and TSOP (Type I) packages. DECODER ...

Page 2

... IS61C256AL PIN CONFIGURATION 28-Pin SOJ A14 1 28 VDD WE A12 A13 A11 A10 I/O7 I/ I/O6 I/ I/O5 I/ I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 Address Inputs CE Chip Enable Input OE Output Enable Input ...

Page 3

... IS61C256AL OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Commercial 0°C to +70°C Industrial –40°C to +85°C DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage ( Input Leakage ...

Page 4

... IS61C256AL READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Output Hold Time OHA CE Access Time t ACS OE Access Time t DOE OE to Low-Z Output t (2) LZOE OE to High-Z Output t (2) HZOE CE to Low-Z Output t (2) LZCS CE to High-Z Output ...

Page 5

... IS61C256AL AC WAVEFORMS READ CYCLE NO. 1 (1,2) ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCS HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 6

... IS61C256AL WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCS t Address Setup Time AW to Write End t Address Hold HA from Write End t Address Setup Time SA WE Pulse Width (OE LOW PWE WE Pulse Width (OE HIGH PWE t Data Setup to Write End ...

Page 7

... IS61C256AL WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ADDRESS OE CE LOW DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) ADDRESS OE LOW CE LOW DATA UNDEFINED OUT D IN Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write ...

Page 8

... IS61C256AL DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current DR t Data Retention Setup Time SDR t Recovery Time RDR Note: 1. Typical Values are measured 5V DATA RETENTION WAVEFORM (CE VDD 4.5V 2. GND 8 Test Condition See Data Retention Waveform = 2.0V, CE ≥ ...

Page 9

... IS61C256AL ORDERING INFORMATION: IS61C256AL Commercial Range: 0°C to +70°C Speed (ns) Order Part Number 10 IS61C256AL-10J IS61C256AL-10JL IS61C256AL-10T IS61C256AL-10TL 12 IS61C256AL-12J IS61C256AL-12JL IS61C256AL-12T IS61C256AL-12TL Industrial Range: –40°C to +85°C Speed (ns) Order Part Number 12 IS61C256AL-12JI IS61C256AL-12JLI IS61C256AL-12TI IS61C256AL-12TLI Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 10

... BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

Page 11

... B — 0.010 C — 0.730 D 20.83 — 0.345 E — 0.305 E1 — 0.287 E2 e Integrated Silicon Solution, Inc. — www.issi.com — ISSI MILLIMETERS INCHES Min. Typ. Max. 32 — — 3.56 — — 0.140 0.64 — — 0.025 — 2.41 — 2.67 0.095 — 0.105 0.41 — ...

Page 12

... C 0.10 0.20 D 7.90 8.10 E 11.70 11.90 H 13.20 13.60 e 0.55 BSC L 0.30 0. Integrated Silicon Solution, Inc. PK13197T28 Rev. B 01/31/ SEATING PLANE Inches Min Max Notes Controlling dimension: millimeters, unless otherwise specified. 0.037 0.047 2. BSC = Basic lead spacing between centers. 0.002 0.008 3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package 0 ...

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