CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
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CD2231
Intelligent Two-Channel LAN and WAN Communications Controller
The CD2231 is a two-channel multi-protocol synchronous/asynchronous communications
controller specifically designed to reduce host-system processing overhead and increase
efficiency in a wide variety of communications applications. The CD2231 is packaged in a 100-
pin MQFP, and offers eight clock/modem pins per channel. The device has two fully
independent serial channels that support asynchronous, asynchronous-HDLC (PPP),
synchronous HDLC/SDLC, SLIP, and MNP 4 protocols at serial data rates up to 256 kbps,
(230.4 kbps in async modes) when clocked by a 35-MHz source.
The device is based on a proprietary on-chip RISC processor that performs all time-critical, low-
level tasks that are otherwise performed by the host system.
The CD2231 boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored
interrupts, and intelligent protocol processing. The on-chip DMA controller provides ‘fire-and-
forget’ transmit support — the host need only inform the CCD2231 of the location of the packet
to be sent. Similarly, on receive, the CD2231 automatically receives a complete packet with no
host intervention or assistance required. The DMA controller also has an ‘Append mode’ for use
in asynchronous applications.
The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer
schemes. Each channel and direction has two active buffers.
The CD2231 can be programmed to interrupt the host at the completion of a frame or buffer. In
applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames
to be divided into multiple buffers.
For applications where a DMA interface is not desired, the device can be operated as an
interrupt-driven or polled device. This choice is available individually for each channel and each
direction. For example, a channel can be programmed for DMA transmit and interrupt-driven
receive.
In either case, 16-byte FIFOs on each channel and in each direction reduce latency time
requirements, making both software and hardware designs less time-critical. Threshold levels on
FIFOs are user-programmable.
Efficient vectored interrupts are another way the CD2231 helps system efficiency. Separate
interrupts are generated for transmit, receive, and modem-signal change with unique user-
defined vectors for each type and channel. This allows very flexible interfacing and fast,
efficient interrupt coding.
As of May 2001, this document replaces the Basis
Communications Corp. document
CL-CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller.
Datasheet
May 2001

CD2231 Summary of contents

  • Page 1

    ... The DMA controller uses a dual-buffer scheme that easily implements simple or complex buffer schemes. Each channel and direction has two active buffers. The CD2231 can be programmed to interrupt the host at the completion of a frame or buffer. In applications where buffers are of a small, fixed size, the dual-buffer scheme allows large frames to be divided into multiple buffers ...

  • Page 2

    ... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The CD2231 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...

  • Page 3

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Contents 1.0 Features ......................................................................................................................... 9 1.1 Benefits ...............................................................................................................11 2.0 Conventions ...............................................................................................................13 3.0 Pin Information 3.1 Pin Diagram.........................................................................................................15 3.2 Pin Functions.......................................................................................................16 3.3 Pin Descriptions ..................................................................................................16 4.0 Register Table 4.1 Memory Map .......................................................................................................20 4.1.1 Global Registers.....................................................................................20 4.1.2 Option Registers.....................................................................................20 4.1.3 Bit Rate and Clock Option Registers......................................................21 4.1.4 Channel Command and Status Registers ..............................................22 4.1.5 Receive Interrupt Registers....................................................................22 4 ...

  • Page 4

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 5.4.1 Bus Acquisition Cycle............................................................................. 43 5.4.2 DMA Data Transfer ................................................................................ 43 5.4.3 Bus Error Handling................................................................................. 44 5.4.4 A and B Buffers and Chaining ................................................................ 45 5.4.5 Transmit DMA Transfer .......................................................................... 46 5.4.6 Synchronous Transmitter Examples ...................................................... 47 5.4.7 Receive DMA Transfer ........................................................................... 49 5.4.8 Transmit DMA Transfer .......................................................................... 52 5.4.9 Receive Buffer Interrupts ....................................................................... 55 5.5 Bit Rate Generation and Data Encoding ............................................................. 57 5 ...

  • Page 5

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 7.5 Transmit Interrupt Service Routine......................................................................87 8.0 Detailed Register Descriptions 8.1 Global Registers..................................................................................................88 8.1.1 Global Firmware Revision Code Register (GFRCR) ..............................88 8.1.2 Channel Access Register (CAR) ............................................................88 8.2 Option Registers..................................................................................................89 8.2.1 Channel Mode Register (CMR) ..............................................................89 8.2.2 Channel Option Register 1 (COR1)........................................................90 8.2.3 Channel Option Register 2 (COR2)........................................................92 8.2.4 Channel Option Register 3 (COR3) — ...

  • Page 6

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 9.0 Electrical Specifications 9.1 Absolute Maximum Ratings .............................................................................. 156 9.2 DC Electrical Characteristics............................................................................. 156 9.3 AC Electrical Characteristics ............................................................................. 157 10.0 Package Specifications 11.0 Ordering Information Example Index ....................................................................................................................................... 169 Bit Index ....................................................................................................................................... 175 Figures 1 Functional Block Diagram ................................................................................... 11 2 Host Read Cycle ................................................................................................. 35 3 Host Write Cycle ................................................................................................. 36 4 Interrupt Acknowledge Cycle ...

  • Page 7

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Tables 1 Pin Descriptions ..................................................................................................17 2 Transmit and Receive Interrupt Service Requests.............................................. and B Buffers Chaining ....................................................................................45 4 Clock Source Select ............................................................................................59 5 Bit Rate Constants, CLK = 20 MHz .....................................................................60 6 Bit Rate Constants, CLK = 25 MHz .....................................................................60 7 Bit Rate Constants, CLK = 30 MHz .....................................................................61 8 Bit Rate Constants, CLK = 35 MHz ...

  • Page 8

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Revision History Revision Date 1.0 5/01 8 Description Initial release. Datasheet ...

  • Page 9

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 1.0 Features • Two full-duplex multi-protocol channels, each capable 256 kbits/second (230.4 kbps in async modes) at 35-MHz CLK • Multi-protocol support: SLIP (serial-line interface protocol), MNP 4, async, async-HDLC (high-level data link control), and HDLC/SDLC (synchronous data link control) on both ...

  • Page 10

    ... DPLL (digital phase locked loop) on each receiver • Two independent timers per channel • Byte-endian-orientation selection pin allows easy interface to 80X86 and 680X0 processors • Eight clock/modem control signals per channel (in addition to TxD and RxD) on CD2231 • Compatible with the CD24XX family of communication controllers 10 Datasheet ...

  • Page 11

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 1. Functional Block Diagram HOST BUS INTERFACE LOGIC HOST INTERFACE ON-CHIP DMA CONTROLLER AND INTERFACE LOGIC 1.1 Benefits • Substantially reduced host CPU overhead means more channels and faster overall throughput. • No time-critical host software enables faster and easier software development. ...

  • Page 12

    ... A clock frequency of 35 MHz is required to obtain maximum bit-rates (60 MHz for CD2481 Rev later versions). 4. 256 kbps in sync mode, 2304 kbps in async modes. Applies to Revision D and later CD2231. 5. UNIX character processing is available in ASYNC only. 6. Compatibility with all pins except those supporting channels 2 and 3 on other family members. These pins are “no connect” ...

  • Page 13

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 2.0 Conventions Abbreviations Symbol Kbit kbits/sec., kbps Kbyte kbytes/sec. kHz k Mbyte MHz The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘ ...

  • Page 14

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Acronym DMA direct-memory access DPLL digital phase-locked loop DRAM dynamic random-access memory DTE data terminal equipment EOF end-of-frame ETC embedded transmit command a FCS frame check sequence FCT flow control transparency FIFO ...

  • Page 15

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 3.0 Pin Information 3.1 Pin Diagram EP[7] 51 EP[8] 52 DSR*[0] 53 CTS*[0] 54 TXCOUT/DTR*[0] 55 RTS*[0] 56 DSR*[1] 57 CTS*[1] 58 TXCOUT/DTR*[1] 59 RTS*[1] 60 EP[9] 61 GND 62 EP[10] 63 N/C 64 N/C 65 EP[11] 66 EP[12] 67 N/C 68 N/C 69 GND 70 A[7] 71 A[6] 72 A[5] 73 A[4] 74 A[3] 75 A[2] 76 A[1] 77 A[0] 78 VDD ...

  • Page 16

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 3.2 Pin Functions A/D[0–15] BUSCLK DATDIR* BYTESWAP IACKOUT* IREQ*[1–3] BGOUT* BGACK* 3.3 Pin Descriptions The following conventions are used in the pin-description tables: • (*) after a name indicates that the signal is active-low • ‘I’ indicates the pin is input-only • ...

  • Page 17

    ... DATA TRANSFER ACKNOWLEDGE*: When the CD2231 is not a bus master, this is an output and indicates to the host when a read or write to the CD2231 is complete. When BR* is driven low by the CD2231, DTACK input which indicates that the system bus is no longer in use ...

  • Page 18

    ... To ensure all CD2231 outputs are high-impedance, either of the following two conditions must be met: the RESET* pin can be driven low, and the TEST pin driven high; or, the CD2231 is kept in the bus idle state (not accessed for read/ write operations nor DMA active), and the TEST pin is driven high. ...

  • Page 19

    ... CARRIER DETECT* [0–1]: This pin is always visible in the MSVR register the CD2231, these functions are separated onto two pins. When used as CD*, this input can be programmed to validate receive data. TRANSMIT CLOCK [0–1]: This pin inputs the transmit clock to the bit rate I generator ...

  • Page 20

    ... Register Table Registers in the CD2231 are either Global or Per-Channel. The column ‘Address mode’ in the memory map on the following pages defines this attribute for each register. Only one set of Global registers exists, and are accessible by the host at any time. Two sets of Per-Channel registers exist, and the set accessible at any one time is determined by the currently active channel number ...

  • Page 21

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Name Description COR6 Channel Option Register 6 COR7 Channel Option Register 7 SCHR1 Special Character Register 1 SCHR2 Special Character Register 2 SCHR3 Special Character Register 3 SCHR4 Special Character Register 4 SCRl Special Character Range low SCRh ...

  • Page 22

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 4.1.4 Channel Command and Status Registers Name Description CCR Channel Command Register STCR Special Transmit Command Register CSR Channel Status Register MSVR-RTS Modem Signal Value Registers MSVR-DTR 4.1.4.1 Interrupt Registers Name Description LIVR Local Interrupt Vector Register ...

  • Page 23

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 4.1.6.1 Modem Interrupt Registers Name Description MPILR Modem Priority Interrupt Level Register MIR Modem Interrupt Register MISR Modem (/Timer) Interrupt Status Register MEOIR Modem End of Interrupt Register 4.1.7 DMA Registers Name Description DMR DMA Mode Register ...

  • Page 24

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Name Description ATBSTS A Transmit Buffer Status BTBSTS B Transmit Buffer Status TCBADRL Transmit Current Buffer Address Lower TCBADRU Transmit Current Buffer Address Upper 4.1.8 Timer Registers Name Description TPR Timer Period Register RTPR Receive Timeout Period Register ...

  • Page 25

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 4.2.2 Option Registers Channel Mode Register (CMR) RxMode TxMode Channel Option Register 1 (COR1) HDLC Mode AFLO ClrDet Asynchronous Mode Parity ParM1 Channel Option Register 2 (COR2) Asynchronous / Async-HDLC / PPP Mode IXM TxlBE HDLC Mode ...

  • Page 26

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Asynchronous Mode EDCDE RngDE SLIP Mode Stop2 0 Channel Option Register 4 (COR4) DSRzd CDzd Channel Option Register 5 (COR5) DSRod CDod Channel Option Register 6 (COR6) Asynchronous Mode IgnCR ICRNL Channel Option Register 7 (COR7) Asynchronous Mode ...

  • Page 27

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Special Character Registers Special Character Register 1 (SCHR1) Special Character Register 2 (SCHR2) Special Character Register 3 (SCHR3) Special Character Register 4 (SCHR4) Special Character Ranges Special Character Range low (SCRl) Special Character Range high (SCRh) ...

  • Page 28

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Receive Clock Option Register (RCOR) TLVal res Transmit Bit Rate Period Register (TBPR) Transmit Clock Option Register (TCOR) ClkSel2 ClkSel1 4.2.4 Channel Command and Status Registers Channel Command Register (CCR) Mode 1 0 ClrCh ...

  • Page 29

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Asynchronous Mode RxEn RxFloff Async-HDLC/PPP Mode RxEn RxFloff SLIP/MNP4 Mode RxEn 0 Modem Signal Value Registers (MSVR) Modem Signal Value Register (MSVR-RTS) Modem Signal Value Register (MSVR-DTR 4.2.5 Interrupt Registers Local Interrupt Vector Register (LIVR) ...

  • Page 30

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Receive Interrupt Status Register (RISR) Receive Interrupt Status Register low (RISRl) HDLC Mode 0 EOF Asynchronous Mode Timeout SCdet2 Async-HDLC / PPP / MNP4 Mode 0 EOF SLIP Mode 0 EOF Receive Interrupt Status Register high (RISRh) ...

  • Page 31

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 4.2.5.2 Transmit Interrupt Registers Transmit Priority Interrupt Level Register (TPILR) Transmit Interrupt Register (TIR) Ten Tact Transmit Interrupt Status Register (TISR) Berr EOF Transmit FIFO Transfer Count (TFTC Transmit Data Register (TDR) ...

  • Page 32

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Bus Error Retry Count (BERCNT) DMA Buffer Status (DMABSTS) TDAlign RstApd 4.2.6.1 DMA Receive Registers A Receive Buffer Address Lower (ARBADRL) A Receive Buffer Address Upper (ARBADRU) B Receive Buffer Address Lower (BRBADRL) B Receive Buffer Address Upper (BRBADRU) ...

  • Page 33

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Asynchronous and HDLC Mode Berr EOF Transmit Current Buffer Address Lower (TCBADRL) Transmit Current Buffer Address Upper (TCBADRU) 4.2.7 Timer Registers Timer Period Register (TPR) Receive Timeout Period Register (RTPR) Receive Timeout Period Register low (RTPRl) ...

  • Page 34

    ... CD2231 in a purely asynchronous bus environment. The CD2231 can act either as a bus master during DMA transfers bus slave device during normal host read and write transfers. Both byte and word transfers are supported in each of the Bus Slave and DMA Bus Master modes ...

  • Page 35

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 2. Host Read Cycle CS* DS* R/W* A/D[0–15] A[0–7], SIZ[0–1] DTACK* DATEN* DATDIR* Datasheet DOUT 35 ...

  • Page 36

    ... Byte and Word Transfers Data can be moved to and from the CD2231 in either byte or word transfers. To accommodate various families of host processors, the BYTESWAP input pin is set to indicate the system byte- ordering scheme. The SIZ pins (SIZ[1, 0]) are used to indicate whether the transfer bytes wide ...

  • Page 37

    ... Data) and RDR (Receive Data) registers provide access to the FIFO buffers for each channel. These registers must not be accessed outside of the proper interrupt context. A write operation to the End of Interrupt registers — REOIR, TEOIR, or MEOIR must be the last access to the CD2231 at the end of this handler routine to return it to its background context. ...

  • Page 38

    ... Groups and Types There are two general reasons for the CD2231 to request service from the host processor — data transfer and exceptional conditions. Furthermore, interrupts are grouped into three categories, each with an associated Interrupt Request signal — IREQ1*, IREQ2*, and IREQ3*. ...

  • Page 39

    ... In other systems that do not use this scheme, the PILR values can be the same or different depending on the specific design. When all of the PILRs contain the same value and multiple IREQn* lines are asserted, the CD2231 imposes the following priority scheme to determine which interrupt request are acknowledged: ...

  • Page 40

    ... If the CD2231 does not have an interrupt asserted, the interrupt acknowledge is passed out on IACKOUT the CD2231 is asserting one or more of its interrupts, but the interrupt priority levels driven on the address bus by the host do not match the contents of the appropriate PILR, this interrupt acknowledge is also passed out on the IACKOUT* ...

  • Page 41

    ... The TxDat and TxEmpty bits in the IER control the generation of transmit FIFO interrupts. The CD2231 initiates an interrupt request for more data when the number of empty bytes in the FIFO is greater than the threshold set. During synchronous operation when the last byte of the frame is transferred to the FIFO, the CD2231 stops asserting transmit interrupts until the frame is sent ...

  • Page 42

    ... When transmitting, the host processor alternately fills the A and B buffers, and commands the CD2231 to transmit the buffers one at a time. When receiving, the CD2231 fills the A and B buffers and informs the host processor when each is ready. ...

  • Page 43

    ... If BGACK* is high when BGIN* goes low, then the bus is free to access step BGACK* is low when BGIN* goes low, then the bus is in use. The CD2231 waits for BGACK high. 5. Once the CD2231 senses that BGACK* is high, the CD2231 waits for the current bus cycle to terminate (DS* and DTACK* high) and then assert BGACK* by driving it low ...

  • Page 44

    ... Bus Error Handling When a bus error is detected during a DMA sequence, the CD2231 terminates the current bus cycle and relinquishes the bus. Any data transfer in the bus ownership cycle is ignored, and the original conditions are restored. A subsequent retry attempt would start again from these original conditions ...

  • Page 45

    ... EOF bit is set, the CRC and closing flag/syn is appended, and the next buffer is again treated as the start of frame. If the EOF bit is not set, the CD2231 treats the buffer as the first part of a larger frame and chains into the next buffer (does not reset CRC); this process continues until a buffer is supplied with the EOF bit set ...

  • Page 46

    ... Append mode transfers are available for Buffer A in Asynchronous mode only. If Buffer A is set to Append mode, the host can enable the CD2231 to transmit data in the buffer before it is completely filled. The CD2231 starts transmitting new data when it is appended to the buffer. ...

  • Page 47

    ... ATBCNT. 3. The host sets up the ATBSTS (‘A’ Buffer Status) register. The EOF bit is set to indicate that there is no chaining. The 2231own bit is set to give ownership to the CD2231. By setting 2231own, the host commands the CD2231 to start transmission. Thus, everything must be ready (starting address, buffer data, and byte count) prior to setting 2231own ...

  • Page 48

    ... ATBSTS register is cleared by the host, indicating that the buffer is not at the end of the chain the end of transmission of this buffer, the CD2231 does not add any CRCs nor end of frame delimiters because there is more data for the current frame. ...

  • Page 49

    ... CD2231 writes the number of bytes stored in the buffer in RBCNT and updates status in RBSTS. This frees the host to take control of this buffer and supply a new buffer in its place. The CD2231 automatically switches to the other buffer whenever one buffer becomes full, or the end of a frame has been reached ...

  • Page 50

    ... The Rbusy bit (DMABSTS[0]) for channel 1 is ‘0’ until a frame starts to be received. When frame data starts coming in, the CD2231 sets Rbusy to notify the host that Buffer B is next. As data bytes are written into the buffer, the current buffer pointer, RCBADR, is updated by the CD2231 ...

  • Page 51

    ... Buffer A ready.) 6. After the CD2231 has received the first link of the frame into Buffer B, it sets the EOB bit and clears the EOF bit. This indicates that the first link in a chain has been received. Also, the CD2231 clears the 2231own bit, and returns ownership of the buffer to the host ...

  • Page 52

    ... CD2231, the value of 40 (for 40 received bytes) is written into the received byte count — BRBCNT. 15. Next, the CD2231 sets the EOB and EOF bits to show that the buffer is complete, and that this is the last link in the chain. 16. The CD2231 optionally interrupts the host with EOF and EOB set in the RISR to indicate that the received frame is complete, and this was the last link in the chain ...

  • Page 53

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 If the above procedure for allocating buffers is used, the CPU has the transmission time of the last buffer to allocate the next to avoid possible underrun. The EOF bit (TISR[6]) is set for the interrupt associated with the last buffer. ...

  • Page 54

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Figure 9. DMA Transmit Buffer Selection Update Descriptor and Set 2231own No More Data to Send ? 54 Start Read DMABSTS to Determine Next Transmit Buffer (NtBuf) Next Buffer 0 1 2231own Bit ? Yes Other Buffer 0 2231own Bit Update ...

  • Page 55

    ... When no more data is found in the append buffer, the CD2231 scans Buffer B for ownership. If Buffer B is owned by the CD2231, the data in that buffer is transmitted uninterrupted; at the end of the transmission, Buffer A count continues to be scanned for new data. ...

  • Page 56

    ... Recommendation: Set TermBuff in REOIR in the receive timeout interrupt service routine. The CD2231 switches to Buffer B. Note: When a receive timeout occurs in Buffer B, the CD2231 pops back to Buffer A, unless the host clears both Ownership Status bits. The above scenarios applies if Buffer B is selected first. ...

  • Page 57

    ... BRG and DPLL Operation Data clocks are generated in the CD2231 by feeding one of a number of clock sources into a programmable divider. The clock source and divisor are separately programmable for each channel and direction by the user. Clock options are programmed in the Transmit Clock Option and Receive Clock Option registers ...

  • Page 58

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller The receive bit rate generator can also be programmed to act as a DPLL . In that mode, the clock select and divisor are programmed near as possible to the nominal receive bit rate. Clock phase adjustments are made by the DPLL logic to lock to the incoming datastream. The receive bit clock is an optional input to the transmitter ...

  • Page 59

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 10. Bit Rate Generator/DPLL System Clock 8 Clk 0 32 Clk 1 128 Clk 2 512 Clk 3 2048 Clk 4 RXCIN or TXCIN RX bit clk (for TX BRG only) Receive Clock Option Register (RCOR) TLVal res Transmit Clock Option Register (TCOR) ...

  • Page 60

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Table 4. Clock Source Select (Sheet ClkSel2 ClkSel1 Table 5. Bit Rate Constants, CLK = 20 MHz Bit Rate 50 110 150 300 600 1200 2400 3600 4800 7200 9600 19200 38400 56000 64000 NOTE: All divisors are in hexadecimal ...

  • Page 61

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Table 6. Bit Rate Constants, CLK = 25 MHz (Sheet Bit Rate 19200 38400 56000 64000 76800 NOTE: All divisors are in hexadecimal. Table 7. Bit Rate Constants, CLK = 30 MHz Bit Rate 110 150 300 600 ...

  • Page 62

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Table 8. Bit Rate Constants, CLK = 35 MHz (Sheet Bit Rate 4800 7200 9600 19200 38400 56000 64000 76800 115200 12800 134400 NOTE: All divisors are in hexadecimal. Transmit and receive data can be encoded and decoded in NRZ, NRZI, or Manchester formats. For NRZI, at the start of transmission, a learning datastream of contiguous zeros achieves bit synchronization ...

  • Page 63

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 The following equation computes the divisor value: bit rate divisor Figure 11. Data Encoding Figure 12. Transmit Data With External Clock In NOTE: When using the external receive clock in Receive mode, data is sampled on the low-to-high- going edge of RXCIN ...

  • Page 64

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Table 9. Data Clock Selection Using External Clock Bit Rate 50 110 150 300 600 1200 2400 3600 4800 7200 9600 19200 38400 56000 64000 76800 115200 128000 5.6 Hardware Configurations To demultiplex the A/D[15:0] bus into separate address and data buses, external buffers and latches are required. To reduce external circuitry, these external devices can be shared in multi– ...

  • Page 65

    ... D[0–15] pins from either half of the 32-bit bus. The A[1] address pin determines if the lower or upper half of the data bus is in use for a particular bus cycle. The CD2231 always drives all 16 data bits during a register-read or DMA-write operation, regardless of the size of the actual transfer. ...

  • Page 66

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Table 10. DTE Connections CD2231 RXD TXD RTS* CTS* DSR* TXCOUT/DTR* RXCIN TXCIN RXCOUT CD* Table 11 shows the recommended DCE (data communications equipment) connections between the CD2231 and RS-232C standard interfaces. Table 11. DCE Connections ...

  • Page 67

    ... Frame Check Sequence The FCS is a 16-bit standard computation used in HDLC, and defined in ISO 3309. This FCS algorithm is the same that is used with the synchronous HDLC operation of the CD2231. The basic characteristics of the FCS are the following: Accumulation: FCS computation starts after the opening flag and continues to the closing flag. ...

  • Page 68

    ... DMA transfers or Good Data interrupts, and then an EOF (end of frame) interrupt is generated. The CRC can be either validated or ignored. If the CD2231 does not check the CRC passed onto the host. A validated CRC can be discarded or passed onto the host for diagnostic purposes. The next non-flag/abort character restarts the process ...

  • Page 69

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 6.2 PPP (Point-to-Point Protocol) Mode 6.2.1 Character Format The PPP mode uses the async-HDLC character format, which is fixed as one start bit, eight data bits, and one stop bit. There is no parity bit. The character format is as shown in Using the bit definitions from the standard format D8 the LSB. Characters are identified as either bits (D1– ...

  • Page 70

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 6.2.4 Transparency Transparency means that there is a protocol method to prevent confusion and ambiguity between control characters and data characters in the frame. For PPP mode, there is a control-escape mechanism. Specific characters are identified as ‘control mapped’ ...

  • Page 71

    ... Section Async-HDLC and PPP protocols have minimum frame size requirements. However, the CD2231 devices makes no requirement of a minimum frame size. The frame opens and ends with a flag (7E). The device complies with this in transmit, and requires opening and closing flags on the receiver. The closing flag from a preceding frame can be the same flag as the opening flag of the next frame ...

  • Page 72

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 6.2.6.3 Transmission of Abort When commanded through a bit in the STCR (Special Transmit Command register), the device ends the transmission of the current frame with an abort sequence of 7D–7E. After executing the abort, the device clears the STCR. The rules for shared flag transmission in followed for the trailing flag (7E) of the abort sequence (7D– ...

  • Page 73

    ... RFC-1055 suggests that when other characters are encountered, the ‘ESC’ should be discarded and the second character should be kept unmodified. The CD2231 follows this convention. The SLIP protocol prohibits in-band flow control. As such, the CD2231 does not respond to XON and XOFF characters in any special way, they are treated as normal data. 6.3.2 Debugging Aids For debug purposes, the CD2231 can send the sequence ‘ ...

  • Page 74

    ... MNP4 except for the two start and escape characters. The CD2231 uses two Special Character registers (SCHR1 and SCHR2) to hold the definition of the start and escape characters. There is no mode selection within the CD2231 that allows it to determine whether ARAP 1.0 or ARAP 2.0 environment. It builds and detects frames using the values in the two Special Character registers ...

  • Page 75

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 18. ARAP 2.0 Frame Start Flag SOH ESC STX data NOTE: The DLE (ARAP 1.0) and ESC (ARAP 2.0) characters in the middle of the data stream, indicated by the ‘T’ column, are inserted for transparency and thus not included in the FCS calculation. ...

  • Page 76

    ... XOFF due to the threshold being exceeded. For this reason, the user should not use the Send Special Character command in the STCR (Special Transmit Command register) to send XON/ XOFF characters because the CD2231 does not keep track of flow control characters that it did not send automatically. The result could cause confusion on the other end of the connection due to conflicting flow control commands ...

  • Page 77

    ... CTS For example, if the CD2231 is designed to be DCE and automatic out-of-band flow control is desired, connect the DTR pin to the remote CTS input. If the CD2231 used as the DTE side, then connect the CD2231 CTS output to the remote CTS input. Note that if automatic out-of-band flow control is implemented, the activity of the DTR and DSR pins do not implement the function assigned to those signal names by the signaling conventions of the CCITT and other standards organizations ...

  • Page 78

    ... Special Character Transmission Selected special characters can be sent preemptively by setting the SndSpc (Send Special Character Command) bit in the STCR. The CD2231 channel acknowledges the command by clearing the STCR. Along with the SndSpc bit, the host needs to set-up the three Special Character Select (SSPC0, SSPC1, SSPC2) bits, also in the STCR, to select which character sent ...

  • Page 79

    ... But overrun condition occurred after a special character is detected, the new character is lost and the overrun status is set. In this condition, the CD2231 gives both an overrun exception and a special character recognition status. 6.5.6 Special Character Range The Special Character Range low and high (SCRl and SCRh) registers define an inclusive range for special character recognition in Asynchronous mode ...

  • Page 80

    ... In Asynchronous mode possible to transmit and receive less than 8 bits per character. There can bits per character. For HDLC mode, there are always 8 bits per character transmitted. The CD2231 transmits only byte-aligned frames. The CD2231 receives HDLC frames using transfers of 8 bits per character, except for the last character received before the FCS ...

  • Page 81

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 19. CD2231 Receive Character Processing Character Received N Error? Y ISTRIP COR7[7] Y FCErr COR7[5] N LNE COR7[6] Previous Y CHAR = LNXT N ISTRIP COR7[7] N SCDE COR3[4] N ESCDE COR3[ Datasheet Y Zero Bit Zero Bit 7 For Special ...

  • Page 82

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Figure 19. CD2231 Receive Character Processing (Continued CHAR = BREAK Y Process Break Options IgnBrk NBrkInt Done 82 COR6[4:3] Action Exception interrupt Discard character Replace with 0 Process Parity Options ParMrk INPCK ParInt ...

  • Page 83

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 19. CD2231 Receive Character Processing (Continued) B RDE COR3[6] N CR/NL Y Options COR6[ CHAR = FF N Datasheet SCRl< Exception CHAR< Interrupt SCRh N Y Discard CHAR = Char Process Translation Options CHAR to FIFO Y ParMrk ...

  • Page 84

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 7.0 Programming Examples This section provides some examples of the CD2231 programming. Included are examples of global and per-channel initialization, and two interrupt service routines. The code is written in Borland Turbo C . Figure 20. Initialization Sequence for the CD2231 ‘ ...

  • Page 85

    ... The TPR (Timer Prescale register) loads the dividing counter that inputs each of the other timers in the CD2231. The DMA Mode register and the Bus Error Count register are used in DMA modes only. After the global portion is done, the Per-Channel registers need to be initialized ...

  • Page 86

    ... The DMABSTS register shows which buffer the CD2231 expects to use next. Fill the descriptor registers for that buffer, including the 2231own bit and return. The last access to the CD2231 during the service routine is the REOIR. int risrl = inportb( RISRL ); // low status int ch = inportb( RIR ) & ...

  • Page 87

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 } else { } } } outportb( REOIR, ZERO ); 7.5 Transmit Interrupt Service Routine This example code is a transmit interrupt service handler example. When using a synchronous protocol, transmitters must declare an end of frame if an underrun occurs. If the end of buffer is encountered before data is transferred by this interrupt service, then the Notrans bit (TEIOR[3]) should be set along with EOF (TEIOR[6]) ...

  • Page 88

    ... This register serves two functions in providing the host with information about the CD2231. When a hardware RESET* signal software RESET ALL command is issued through either of the two Channel Command registers, it initializes the CD2231 and zeroes this register at the start of the initialization. At the end of the initialization, the CD2231 writes its firmware revision code to the GFRCR ...

  • Page 89

    ... DMA Bit 6 Transmit Transfer mode 0 – Interrupt 1 – DMA Bits 5:3 Reserved – must be ‘0’. Bits 2:0 Protocol mode select If these options are changed, an initialize command must be given to the CD2231 through the Channel Command register. Datasheet C0 Channel number 0 Channel 0 1 Channel 1 ...

  • Page 90

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.2.2 Channel Option Register 1 (COR1) 8.2.2.1 COR1 — HDLC Mode Register Name: COR1 Register Description: Channel Option Register 1 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 AFLO ClrDet AdMd1 If any options specified in this register are changed, an initialize command must be given to CD2231 through the Channel Command register ...

  • Page 91

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 8.2.2.2 COR1 — Asynchronous Mode Register Name: COR1 Register Description: Channel Option Register 1 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Parity ParM1 ParM0 Bit 7 Parity 1 = odd parity 0 = even parity Bits 6:5 Parity mode 1 and 0 ...

  • Page 92

    ... Bit 2 RTS automatic output enable When set, if the channel is enabled, the CD2231 automatically asserts the RTS* out- put when it has characters to send. When Idle-in Mark mode is selected, RTS* is asserted prior to opening flags and remains asserted until after a closing flag has been transmitted ...

  • Page 93

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 If IXM = 0, transmission is resumed only after the receipt of an XON character or a transmit enable command by the CCR (Channel Command register). If IXM = 1, transmission is resumed after the receipt of any character or a transmit enable command by the CCR. ...

  • Page 94

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Bit 3 RLM – Remote Loop Back mode RLM = 1 enables Remote Loopback mode RLM = 0 disables Remote Loopback mode Bit 2 RtsAO – RTS automatic output enable If RtsAO = 1, then the RTS* output pin remains enabled during DMA or character bursts from the transmit FIFO ...

  • Page 95

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 . npad3 8.2.4.1 MNP 4 Mode Register Name: COR3 Register Description: Channel Option Register 3 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Stop2 FCSApd RxChk SLIP, MNP4, and Automatic In-Band Flow Control modes are only available on Revision B and later devices ...

  • Page 96

    ... Alt1 FCSPre In Synchronous mode, COR3 is used to specify the learning pattern (pad character) sent by the CD2231 to synchronize the DPLL at the remote end. The pad character (00h or AAh) sent depends on the kind of encoding used. Bit 7 Sends pad character( CD2231 sends pad character(s) before sending flag when coming out of the Idle- in Mark mode ...

  • Page 97

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 8.2.4.3 SLIP Mode Register Name: COR3 Register Description: Channel Option Register 3 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Stop2 0 0 SLIP, MNP4, and Automatic In-Band Flow Control modes are only available on Revision B and later devices ...

  • Page 98

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Bit 5 FCT – Flow Control Transparency mode 0 = Flow control characters received are passed to the host by receive exception interrupts Flow control characters received are not passed to the host. This bit has no effect unless both TxIBE (COR2[6]) and SCDE (COR3[4]) are set. ...

  • Page 99

    ... FIFO is greater than the specified threshold. An end of frame also initiates a receive transfer. For transmit operation, the CD2231 attempts to refill the transmit FIFO when the empty space in the FIFO is greater than the set threshold. In synchronous frame transmissions, the CD2231 stops refilling the transmit FIFO once the last character in the frame transfers to the FIFO ...

  • Page 100

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Note: Do not use the STCR (Special Transmit Command register) to send XON and XOFF characters while using automatic in-band flow control. Bits 3:0 Receive flow control FIFO threshold These four bits define the threshold for automatic flow control activation based on the contents of the receive FIFO ...

  • Page 101

    ... This provides a mechanism to transfer flow control and special characters as normal data, without invoking flow control action in the CD2231, and without generating special interrupts. The LNext character is defined in the LNXT register, and when processed, is always passed to the host CPU as normal data. ...

  • Page 102

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 1 = All receive characters, even those with errors, are processed for special charac- ter/flow control processing. Bits 4:2 Reserved – must be ‘0’. Bits 1:0 Transmit processing for CR and NL; these bits define Translation mode when CR and/or NL are present in the transmit data ...

  • Page 103

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 SCHR1 = XON SCHR2 = XOFF In addition to the SCDE and TxIBE bits, if the FCT bit (COR3) is set when flow control characters are received, they are stripped from the data stream. MNP 4 Mode SCHR1 holds the start character. ...

  • Page 104

    ... Bit 6 Bit 5 This register defines the LNext character. If the LNext function is enabled (COR7[6]), the CD2231 examines received characters and compare them against this value match occurs, this character and the following are placed in the FIFO without any special processing. In effect, the LNext function causes the CD2231 to ignore characters with special meaning, such as flow control characters. There are two exceptions: a ‘ ...

  • Page 105

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 8.2.12 Receive Frame Address Registers — HDLC Sync Mode Only 8.2.12.1 Receive Frame Address Register 1 (RFAR1) Register Name: RFAR1 Register Description: Receive Frame Address Register 1 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 8 ...

  • Page 106

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.2.13 CRC Polynomial Select Register (CPSR) Register Name: CPSR Register Description: CRC Polynomial Select Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit Bits 7:1 Reserved – must be ‘0’. Bit 0 Polynomial select 0 = CRC V.41 polynomial (normally used for HDLC protocol and preset to 1’ ...

  • Page 107

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 8.2.14.3 Transmit Special Mapped Character 3 (TSPMAP3) Register Name: TSMAP3 Register Description: Special Mapped Transmit Character 3 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 The three TSPMAP registers are used to provide control character escape processing on characters outside the 00– ...

  • Page 108

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.2.15.3 Transmit Async Control Character Map 2 (TXACCM2) Register Name: TXACCM2 Register Description: Transmit Async Control Character Map 2 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Char. 17 Char. 16 Char. 15 8.2.15.4 Transmit Async Control Character Map 3 (TXACCM3) ...

  • Page 109

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 8.2.16.2 Receive Async Control Character Map 1 (RXACCM1) Register Name: RXACCM1 Register Description: Receive Async Control Character Map 1 Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Char. 0F Char. 0E Char. 0D 8.2.16.3 Receive Async Control Character Map 2 (RXACCM2) ...

  • Page 110

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.3 Bit Rate and Clock Option Registers 8.3.1 Receive Baud Rate Generator Registers 8.3.1.1 Receive Baud Rate Period Register (RBPR) Register Name: RBPR Register Description: Receive BitRate Period Default Value: x’81 Access: Byte Read/Write Bit 7 ...

  • Page 111

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Dpllmd1 Bits 2:0 These three bits select the clock source for the receive baud rate generator or DPLL. NOTE: See the description of clock options in 8.3.2 Transmit Baud Rate Generator Registers 8.3.2.1 Transmit Baud Rate Period Register (TBPR) ...

  • Page 112

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.3.2.2 Transmit Clock Option Register (TCOR) Register Name: TCOR Register Description: Transmit Clock Option Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 ClkSel2 ClkSel1 ClkSel0 This register controls the transmit bit rate generator and Local Loopback mode. ...

  • Page 113

    ... The various command and control bits in this register perform largely independent functions. The host can assert multiple command bits to achieve the desired effect. The CD2231 clears the register to zero after it accepts and acts on a host command. The host must verify that the contents of this register are zero prior to issuing a new command ...

  • Page 114

    ... FIFO and clears receive status in the CSR, except for the RcvEn bit. ClrRcv clears receive DMA buffer status in ARBSTS, BRBSTS, and Receive Status bits in DMABSTS. Clearing the 2231own bits in both the Receive Buffer Sta- tus registers means that DMA buffers have to be returned to the CD2231 before receive transfers begin again. 114 ...

  • Page 115

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 For Synchronous modes, this command puts the receiver back into Syn/Flag Hunt mode. Bit 3 Clear transmitter command This command only affects the trasmitter and is only available on Revision C and later devices and is only effective in asynchronous protocols. It resets all transmitter functions like a combination of clear channel, initialize channel and transmit com- mands ...

  • Page 116

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Bit 0 Xoff – Send XOFF Causes the transmission of an XOFF (cntl-S or hex 13). The command structure associated with the sndsp Control bit is: sndsp NOTE: The user should not use the send XON/XOFF commands if automatic in-band flow control is enabled (Asynchronous modes only) in COR5 ...

  • Page 117

    ... Bit 7 Bit 6 Bit 5 0 AbortTx AppdCmp The CD2231 clears the register to zero when it accepts a host CPU command. Bit 7 Reserved – must be ‘0’. Bit 6 Abort transmission (HDLC) Terminates the frame currently in transmission with an abort sequence. In DMA mode, all data up to the next EOF is discarded. ...

  • Page 118

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.4.3.1 CSR — HDLC Mode Register Name: CSR Register Description: Channel Status Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 RxEn RxFlag RxFrame Bit 7 Receiver enable 0 = Receiver is disabled 1 = Receiver is enabled Bit 6 Rx flag ...

  • Page 119

    ... Transmitter is disabled 1 = Transmitter is enabled Bit 2 Transmit flow off 0 = Normal 1 = The CD2231 has been requested by the remote to stop transmission. This bit is reset when the CD2231 receives a request to resume transmission, or when the trans- mitter is enabled or disabled, or the channel is reset. Bit 1 Transmit flow Normal 1 = The CD2231 has been requested by the remote to resume transmission ...

  • Page 120

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller When clear, the remote station is not requested to stop transmission. RxFloff remains set until the host issues an STCR command to send an Xon. Bit 5 RFram – Receive frame status When set, a frame is being received. When clear, no frame is being received. ...

  • Page 121

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Bit 3 TxEn – Transmitter enabled status When set, the transmitter is enabled. When clear, the transmitter is disabled. Bit 2 Reserved – must be ‘0’. Bit 1 TFram – Transmit frame status When set, a frame is being transmitted. ...

  • Page 122

    ... Bits 1:0 Interrupt type. These two bits indicate the group/type of interrupt occurring. IT[1:0] Note: Note that because the CD2231 provides a unique Local Interrupt Vector register for each channel, the host has the option to include the channel number within the interrupt vector. 122 Bit 4 ...

  • Page 123

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 8.5.1.2 Interrupt Enable Register (IER), Non-PPP Modes Register Name: IER Register Description: Interrupt Enable Default Value: x’00 Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Mdm 0 RET Bit 7 Modem pin change detect Master interrupt enable for modem change detect functions. The host can select which modem pins are monitored for input change and select either or both direc- tions of change by programming the change detect option bits in COR4 and COR5 ...

  • Page 124

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Bit 7 Modem pin change detect Master interrupt enable for modem change detect functions. The host can select which modem pins are watched for input change and select either or both directions of change by programming the change detect option bits in COR4 and COR5. A Group1 type interrupt (see LIVR description) is generated from this enable ...

  • Page 125

    ... Bit 5 This register must be initialized by the host to contain the codes that are presented on the address bus by the host system to indicate which of the three CD2231 interrupt types (modem, transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2231 compares bits 0–6 in this register with A[0–6] to determine if the acknowledge level is correct. The value programmed in the MSB of the register has no effect on the IACK cycle ...

  • Page 126

    ... Reserved – always returns ‘0’ when read. Bits 3:2 Rvct [1:0] Receive vector bits are set by the CD2231 to provide the lower two bits of the vector supplied to the host CPU during an interrupt acknowledge cycle. Receive good data vector is decoded as follows: Rvct [ and Rvct [ Receive exception vec- tor is decoded as follows: Rvct [ and Rvct [ ...

  • Page 127

    ... CRC error on current frame. Bit 3 Overrun error – indicates that new data has arrived, but the CD2231 FIFO or holding registers are full. The new data is lost, and the overrun indication is flagged on the last character received before the overrun occurred. In HDLC and Bisync modes, the remainder of a frame, following an overrun, is discarded ...

  • Page 128

    ... Bits 6:4 Special character detect SCdet[2:0] Bit 3 Overrun error – indicates that new data has arrived, but the CD2231 FIFO or holding registers are full. The new data is lost and the overrun indication is flagged on the last character received before the overrun occurred. Bit 2 Parity error – ...

  • Page 129

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Bit 6 EOF – End of frame The EOF bit indicates that a valid end of frame (7E) character has been received, and the 7E was not preceded by a 7D. Bit 5 RxAbt – Receive abort The rxabt bit indicates that an abort sequence (7D–7E) has been received. ...

  • Page 130

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Bit 5 RxAbt – Receive abort The rxabt bit indicates that an abort sequence (7D–7E) has been received. Bit 4 Unused; returns ‘0’ when read. Bit 3 OE – Overrun error The OE bit indicates that the receiver buffer and FIFO have been overrun. At least one new character has been received, but lost since there was no room available in the receiver buffer and/or FIFO ...

  • Page 131

    ... Access: Byte Write Only Bit 7 Bit 6 Bit 5 TermBuff DiscExc SetTm2 The CD2231 interprets values written to this register at the completion of all receive interrupts. Bit 7 Terminate current DMA buffer If this bit is set, the current receive buffer is terminated and data transfer is switched Datasheet Bit 4 Bit 3 ...

  • Page 132

    ... Bit 5 TermBuff DiscExc SetTm2 The CD2231 interprets values written to this register at the completion of all receive interrupts. Bit 7 Terminate current DMA buffer If this bit is set, the current receive buffer is terminated and data transfer is switched to the other buffer. This bit should only be set in response to an async exception interrupt ...

  • Page 133

    ... Bit 5 This register must be initialized by the host to contain the codes that are presented on the address bus by the host system to indicate which of the three CD2231 interrupt types (modem, transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2231 compares bits 0–6 in this register with A[0–6] to determine if the acknowledge level is correct. The value programmed in the MSB of the register has no effect on the IACK cycle ...

  • Page 134

    ... Reserved – always returns ‘0’ when read. Bits 3:2 Tvct [1:0] Transmit Vector bits are set by the CD2231 to provide the lower two bits of the vec- tor supplied to the host CPU during an interrupt acknowledge cycle. Transmit vector is decoded as follows: Tvct [ and Tvct [ ...

  • Page 135

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 8.5.3.3 Transmit Interrupt Status Register (TISR) Register Name: TISR Register Description: Transmit Interrupt Status Default Value: x’00 Access: Byte Read only Bit 7 Bit 6 Bit 5 Berr EOF EOB When the host receives a transmit interrupt, the following status is provided in this register: Bit 7 Berr – ...

  • Page 136

    ... SetTm2 The Transmit End of Interrupt register must be written to by the corresponding host interrupt service routine to signal to the CD2231 that the current interrupt service is concluded. This must be the last access to the CD2231 during an interrupt service routine. Writing to this register generates an internal end of interrupt signal which pops the CD2231 interrupt context stack. ...

  • Page 137

    ... Bit 5 This register must be initialized by the host to contain the codes that are presented on the address bus by the host system to indicate which of the three CD2231 interrupt types (modem, transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2231 compares bits 0–6 in this register with A[6:0] to determine if the acknowledge level is correct. The value programmed in the MSB of this register has no effect on the IACK cycle ...

  • Page 138

    ... Reserved – always returns ‘0’ when read. Bits 3:2 Mvct [1:0] Modem Vector bits are set by the CD2231 to provide the lower two bits of the vector supplied to the host CPU during an interrupt acknowledge cycle. Modem vector is decoded as follows: Mvct [ and Mvct [ ...

  • Page 139

    ... MISR, to the high byte of General Timer 1. At the end of an interrupt service routine, the user can set the timer by setting a timer value in the Modem Interrupt Status register. When the timer reaches ‘0’, the CD2231 generates a modem/timer group interrupt to the host. Bits 3:0 Reserved – must be ‘0’. ...

  • Page 140

    ... DMA operations suspended to the buffer in error, until the interrupt is processed by the host CPU. When this register contains a non-zero value and when a bus error occurs, the CD2231 retries the same DMA operation and decrements the register value by one. When the value reaches zero, the next bus error causes an interrupt, at that time a new count can be loaded by the host CPU ...

  • Page 141

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 0 = Append buffer is not in use Append buffer is in use. Bit 3 Ntbuf Next transmit buffer 0 = Buffer A is the next transmit buffer Buffer B is the next transmit buffer. This bit is toggled when transmission starts from a buffer, that is, when data is first read from Buffer A, the bit is set to indicate that Buffer B is next ...

  • Page 142

    ... Bit 13 Bit 7 Bit 6 Bit 5 These registers contain the start addresses of two external buffers that are used by the CD2231 to store the next two receive data blocks. They are written to by the host and copied internally to control the data transfer to the memory. 142 ...

  • Page 143

    ... Bit 6 Bit 5 These registers contain the number of bytes stored in the external data buffers by the CD2231. The count is updated after a block of data is moved to memory and the buffer is terminated. As initially written by the host, the register contains the number of bytes the buffer can hold. ...

  • Page 144

    ... Ownership of the transfer buffer (set by the host CPU and cleared by the CD2231 Buffer not free to be used by CD2231 Buffer free to be used by CD2231. When the Buffer Complete bit is set by the CD2231, the buffer is free for the host to process. (RBCNT information is updated to the number of bytes available in the buffer, and a new buffer can be allocated.) 8.6.4.9 Receive Current Buffer Address Register — ...

  • Page 145

    ... These registers contain the address of the current DMA buffer being used for receive data, updated at the end of receive data transfers. These registers are for the private use of the CD2231 to manage DMA transfers. In Asynchronous mode, the host can read this register during a receive exception interrupt to determine how much data is in the buffer ...

  • Page 146

    ... Bit 7 Bit 6 Bit 5 These registers contain the start addresses of two external buffers that are used by the CD2231 to transmit the next data blocks. They are written to by the host and copied internally to control the data transfer from the memory to the CD2231 FIFO. ...

  • Page 147

    ... ATADR and ATCNT as normal, but when new data is appended to the buffer, the ATBCNT/BTBCNT (Transmit Buffer Count) can be updated. When the A buffer is used in Append mode, the CD2231 does not set the EOB bit. When the host has completed use of the buffer, it must issue the append complete command through STCR. The CD2231, upon transmitting the last characters from the buffer, sets EOB, thus allowing the host to allocate a new transmit buffer ...

  • Page 148

    ... Address) and ATBCNT/BTBCNT (Transmit Buffer Count) registers, and then set the 2231own bit. If the CD2231 is to generate and send the CRC for the frame, the CRC bit in COR1 must be set. If the buffer contains the end of a frame, the EOF bit must also be set. When the buffer has been sent, the EOB bit is set by the CD2231, and 2231own is reset, allowing a new buffer to be allocated ...

  • Page 149

    ... Bit 0 2231own – Ownership of the transmit buffer (set by the host and cleared by the CD2231 Buffer is owned by the host, and not ready for use by the CD2231 Buffer is owned by the CD2231, and is ready for use by the CD2231. 8.6.5.10 A Transmit Buffer Status (ATBSTS) — HDLC Mode Register Name: ATBSTS Register Description: Transmit Buffer ‘ ...

  • Page 150

    ... EOF EOB This register contains the status of the associated transmit buffer, and it enables successive buffers to be passed between the host and the CD2231. Status bits within the register are defined as: Bit 7 Bus error (set by the CD2231 and cleared by the host CPU bus error Bus error occurred on the last transfer ...

  • Page 151

    ... EOF EOB This register contains the status of the associated transmit buffer, and it enables successive buffers to be passed between the host and the CD2231. Status bits within the register are defined as: Bit 7 Bus error (set by the CD2231 and cleared by the host CPU bus error Bus error occurred on the last transfer ...

  • Page 152

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.6.5.14 Transmit Current Buffer Address Register — Lower (TCBADRL) Register Name: TCBADRL Register Description: Current Transmit Buffer Address, lower word Default Value: x’0000 Access: Word Read Only Bit 15 Bit 14 Bit 13 Bit 7 Bit 6 Bit 5 8.6.5.15 Transmit Current Buffer Address Register — ...

  • Page 153

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 This register provides the initialization value for the timer prescaler that is itself clocked by a prescaled clock equal to system clock various on-chip timers (including RTPR, TTR, and the general timers available to the host in the Synchronous modes) ...

  • Page 154

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 8.7.3 General Timer 1 (GT1) Sync Modes Only Register Name: GT1 Register Description: General Timer 1 Default Value: x’00 Access: Word Read/Write Bit 15 Bit 14 Bit 13 Bit 7 Bit 6 Bit 5 8.7.3.1 General Timer 1 low (GT1l) Sync Modes Only ...

  • Page 155

    ... Access: Byte Read only Bit 7 Bit 6 Bit 5 This Asynchronous mode timer is managed by the CD2231 to implement embedded transmit delays when that option is used by the host (see description of Channel Option Register 2). This register should not be modified by the host under any circumstances. Datasheet Bit 4 ...

  • Page 156

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 9.0 Electrical Specifications Note: Verify with your local sales office that you have the latest datasheet before finalizing a design. 9.1 Absolute Maximum Ratings Operating ambient temperature (T Storage temperature ............................................................................ 150 C All voltages with respect to ground .............................. 0 ...

  • Page 157

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 9.3 AC Electrical Characteristics Symbol t Period of CLK input (35 MHz maximum) PERIOD t CLK high to BUSCLK high 1 t CLK high to BUSCLK low 2 Bus Arbitration t CLK high to BGACK* tristate 11 t BGIN* low to address valid 12 t Address hold after CLK high ...

  • Page 158

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Symbol t Reserved 42 t Reserved 43 t R/W* setup to CLK high 44 t CLK high to data valid 45 t Data setup time to CLK high 46 t Data hold time after CLK high 47 t Address setup time to CLK high ...

  • Page 159

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 21. CLK / BUSCLK / RESET* TIming Relationship t PERIOD CLK t BUSCLK RESET* During RESET* active period, BUSCLK is held low. BUSCLK will transition high and begin running at one/half CLK frequency on the first rising edge of CLK after RESET* is released. ...

  • Page 160

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Figure 22. Slave Read Cycle Timing CLK BUSCLK t 41 DS A[0–7] A/D[0–15] DTACK DATEN* /DATDIR* 160 Datasheet ...

  • Page 161

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 23. Slave Write Cycle Timing CLK BUSCLK t 41 DS A[0–7] A/D[0–15] DTACK DATEN* Datasheet 161 ...

  • Page 162

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Figure 24. Interrupt Acknowledge Cycle Timing CLK BUSCLK t 61 DS*, IACKIN* R/ A[0–7] A/D[0–15] DTACK DATEN*, DATDIR* 162 Datasheet ...

  • Page 163

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 25. Bus Arbitration Cycle Timing CLK BUSCLK BR* BGIN* ADLD* A[0–7] A/D[0–15] AS* AEN*/DATEN*/ DATDIR* BGACK* R/W* In DMA Read cycle, these pins will be tristate; in DMA Write cycle, these pins will be D[0:15]. Datasheet ...

  • Page 164

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Figure 26. Bus Release Timing CLK BUSCLK AS*, DS* A[0–7] A/D[0–15] BGACK* R/W* DATEN*, AEN*, DATDIR* 164 Datasheet ...

  • Page 165

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 Figure 27. DMA Read Cycle Timing CLK BUSCLK A[0–7] A/D[0–15] DTACK* BERR* Datasheet BERR* Timing setup time to CLK rising edge = 10ns hold time after CLK rising edge = 20ns ...

  • Page 166

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller Figure 28. DMA Write Cycle Timing CLK BUSCLK t 24 AS* DS A[0– A/D[0–15] DTACK* BERR* 166 BERR* Timing setup time to CLK rising edge = 10ns hold time after CLK rising edge = 20ns ...

  • Page 167

    ... Intelligent Two-Channel LAN and WAN Communications Controller — CD2231 10.0 Package Specifications 13.90 (0.547) 14.10 (0.555) Pin 1 Indicator Pin 100 Pin 1 0.65 (0.026) 0.95 (0.037) 0.13 (0.005) 0.23 (0.009) 3.40 (0.134) MAX NOTES: 1. Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2. Before beginning any new design with this device, please contact Intel for the latest package information. ...

  • Page 168

    ... CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller 11.0 Ordering Information Example † Contact Intel Corporation for up-to-date information on revisions. 168 SCD223110QCD Communications, Data Part number Internal reference number † Revision Temperature Range Commercial Package Type MQFP (metric quad flat pack) ...

  • Page 169

    Index Numerics 32-bit data bus and C fields 69 abbreviations 13 absolute maximum ratings 156 AC electrical characteristics bus arbitration 157 DMA read 157 DMA write 157 host read/write 157 interrupt acknowledge 158 ACCM (async-control-character map) 70 ...

  • Page 170

    ... I Idle mode 96 Idle-in Mark mode 96 initialization sequence for the CD2231 84 interrupt acknowledge 158 interrupt service requests 39 interrupts 170 acknowledge cycle 38 contexts and channels 37 groups and types 38 ...

  • Page 171

    FCT (flow control transparency) mode 98, 103 Flag Hunt mode 68 Flag mode 67, 68 HDLC mode 90, 92, 96, 118, 127 High-Impedance mode 18 Idle mode 96 Idle-in Mark mode 96 Local Loopback mode 112 Mark mode 67, 68 ...

  • Page 172

    RCBADRU 23, 32, 145 DMA registers BERCNT 23, 32, 140 DMABSTS 23, 32, 140 DMR 23, 31, 139 DMA Transmit registers ATBADRL 23, 32, 145 ATBADRU 23, 32, 146 ATBCNT 23, 32, 147 ATBSTS 24, 32, 147, 148, 149, 150, ...

  • Page 173

    TISR 22, 31, 135 TPILR 22, 31, 133 Remote Loopback mode 93 service routine receive DMA interrupt 86 transmit interrupt 87 setup examples async interrupt 85 HDLC DMA channel 86 SLIP mode 97, 129 SLIP/MNP4 mode 116, 120 ...

  • Page 174

    ...

  • Page 175

    Bit Index Numerics 2231own 143, 147–150 A AbortTx 115, 116–117 AdMd[1:0] 90 AFLO 90 Alt1 96 AppdCmp 117 Append 140, 150 B BA/BB 130, 135 Berr 130, 135, 143, 147–150 Binary 141 Binary address value 141, 142, 144–146, 152 Binary ...

  • Page 176

    F FCErr 101 FCS 96 FCSApd 92, 94, 95 FCSPre 96 FCT 97 FE 128, 129 FIFO threshold 98 Firmware revision code 88 Flag[3:0] 90 Frame 115, 116 Frame Qualification Address [4:0] 105 G Gap[2:0] 131 I ICRNL 100 idle ...

  • Page 177

    RLM 92–93 RngDE 97 RstAll 113 RstApd 140 RTS 121 RtsAO 92–93 Rvct [1:0] 126 Rx flow control threshold 99 RxAbt 127, 128–129 RxChk 94–95 RxCt [4:0] 131 RxD 123 RxEn 118–120 RxFlag 118 RxFloff 118–119 RxFlon 118 RxFrame 118 ...

  • Page 178

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