CD2231 Intel Corporation, CD2231 Datasheet - Page 102

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.2.9
8.2.9.1
8.2.9.2
102
Register Name: SCHR1
Register Description: Special Character Register 2
Default Value: x’00
Access: Byte Read/Write
Register Name: SCHR2
Register Description: Special Character Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 7
Bits 4:2
Bits 1:0
Special Character Registers — Async Modes Only
Special Character registers can be used for detecting specific receive characters in the incoming
data stream, and can be used to transmit characters (by STCR) preempting any data in the transmit
FIFO.
Special Character Register 1 (SCHR1)
Special Character Register 2 (SCHR2)
Asynchronous Mode
Special characters 1 and 2 are used in conjunction with the SCDE bit COR3[4] to detect incoming
characters; when both SCDE and TxIBE (COR2[6]) are set, they define the in-band flow control
characters XON and XOFF.
Bit 6
Bit 6
1 = All receive characters, even those with errors, are processed for special charac-
ter/flow control processing.
Reserved – must be ‘0’.
Transmit processing for CR and NL; these bits define Translation mode when CR
and/or NL are present in the transmit data.
Bit 5
Bit 5
ONLCR
protocol-defined special characters (see below).
protcol-defined special characters (see below).
0
0
1
1
User-defined special character,
User-defined special character,
Bit 4
OCRNL
Bit 4
0
1
0
1
No special action
CR translated to NL
NL translated to the sequence CR NL
CR translated to NL and NL translated to the sequence CR
NL
Bit 3
Bit 3
Bit 2
Bit 2
Motorola Hex Address: x’1F
Motorola Hex Address: x’1E
Bit 1
Bit 1
Intel Hex Address: x’1C
Intel Hex Address: x’1D
Datasheet
Bit 0
Bit 0