CD2231 Intel Corporation, CD2231 Datasheet - Page 137

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

8.5.4
8.5.4.1
8.5.4.2
Datasheet
Register Name: MPILR
Register Description: Modem Priority Interrupt Match
Default Value: x’00
Access: Byte Read/Write
Register Name: MIR
Register Description: Modem Interrupt
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 7
Men
Note: Bit 7 of this register is always read back as ‘0’. When each of the three Priority Interrupt Level
Bit 3
Bits 2:0
Modem Interrupt Registers
Modem Priority Interrupt Level Register (MPILR)
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2231 interrupt types (modem, transmit, or
receive) is being acknowledged when IACKIN* is asserted. The CD2231 compares bits 0–6 in this
register with A[6:0] to determine if the acknowledge level is correct. The value programmed in the
MSB of this register has no effect on the IACK cycle.
The MPILR must contain the code used to acknowledge modem/timer interrupts.
registers is programmed with the same value, they are internally prioritized, with receive as the
highest priority, followed by transmit and modem.
Modem Interrupt Register (MIR)
Bit 7
Bit 6
Mact
Bit 6
Bit 6
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in the Transmit Interrupt Status register. When the timer reaches ‘0’, the
CD2231 generates a modem/timer group interrupt to the host.
No transfer of data
This bit must be set by the host, if no data is transferred to the transmit FIFO during
a data transfer interrupt.
Reserved – must be ‘0’.
Mer
Modem enable is set by the CD2231 to initiate a modem interrupt request sequence.
It is cleared during a valid modem interrupt acknowledge cycle.
Mact
Modem active is set automatically when Men is set, and the Fair Share logic allows
Bit 5
Bit 5
Meo
User-assigned priority match value
Bit 4
Bit 4
0
Mvct [1]
Bit 3
Bit 3
Mvct [0]
Bit 2
Bit 2
Motorola Hex Address: x’EF
Motorola Hex Address: x’E3
Bit 1
Bit 1
Intel Hex Address: x’ED
0
Intel Hex Address: x’E1
Mcn [0]
Bit 0
Bit 0
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