CD2231 Intel Corporation, CD2231 Datasheet - Page 138

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.5.4.3
138
Register Name: MISR
Register Description: Modem Interrupt Status
Default Value: x’00
Access: Byte Read/Write
DSRChg
Bit 7
Bit 5
Bit 4
Bits 3:2
Bit 1
Bit 0
Modem (/Timer) Interrupt Status Register (MISR)
When the host receives a modem interrupt, the following status is provided in this register:
Bit 7
Bit 6
Bit 5
Bits 4:2
Bit 1
Bit 0
CDChg
Bit 6
the assertion of a modem interrupt request. It is cleared when the host CPU writes to
the Modem End of Interrupt register.
Meo
Modem end of interrupt is set automatically when the host CPU writes to the Modem
End of Interrupt register while in a modem interrupt routine.
Reserved – always returns ‘0’ when read.
Mvct [1:0]
Modem Vector bits are set by the CD2231 to provide the lower two bits of the vector
supplied to the host CPU during an interrupt acknowledge cycle. Modem vector is
decoded as follows: Mvct [1] = 0, and Mvct [0] = 1.
Reserved – always returns ‘0’ when read.
Mcn [0]
Modem channel number is set by the CD2231 to indicate the channel requiring
modem interrupt service.
DSR changed
A logic ‘1’ indicates that a change has been detected on the DSR* input. The change
detect is programmed in COR4 and COR5.
CD changed
A logic ‘1’ indicates that a change has been detected on the CD* input. The change
detect is programmed in COR4 and COR5.
CTS changed
A logic ‘1’ indicates that a change has been detected on the CTS* input. The change
detect is programmed in COR4 and COR5.
Unused; returns ‘0’ when read
General Timer 2 timed-out (count reaches zero before being reset or disabled).
General Timer 1 timed-out (count reaches zero before being reset or disabled).
CTSChg
Bit 5
Men
0
1
1
0
0
Mact
Bit 4
0
0
1
1
0
0
Meo
0
0
0
0
1
Bit 3
0
Sequence of Events
Idle
Modem interrupt requested, but not asserted
Modem interrupt asserted
Modem interrupt acknowledged
Modem interrupt service routine completed
Bit 2
0
Motorola Hex Address: x’8B
Timer2
Bit 1
Intel Hex Address: x’88
Datasheet
Timer1
Bit 0