CD2231 Intel Corporation, CD2231 Datasheet - Page 151

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

8.6.5.13
Datasheet
Register Name: BTBSTS
Register Description: Transmit Buffer ‘B’ Status
Default Value: x’00
Access: Byte Read/Write
Bit 7
Berr
B Transmit Buffer Status (BTBSTS) — Async Mode
This register contains the status of the associated transmit buffer, and it enables successive buffers
to be passed between the host and the CD2231. Status bits within the register are defined as:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 6
EOF
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Bus error (set by the CD2231 and cleared by the host CPU)
0 = No bus error.
1 = Bus error occurred on the last transfer; the suspect address is available in
TCBADR.
End of frame (set and cleared by host CPU)
0 = This buffer is not the last in frame/block.
1 = This buffer is the last in frame/block.
The end of a transmit buffer has been reached. This bit is used only for DMA sup-
ported transfer. The end of one of the host supplied transmit buffers has been
reached. This bit is set by the CD2231 and cleared by the host CPU.
Reserved – must be ‘0’.
Append (Asynchronous mode only; set and cleared by the host CPU)
0 = No data is appended to the buffer.
1 = Data can be appended to buffer after tx started.
Reserved – must be ‘0’.
Interrupt
0 = No interrupt required after the buffer is sent.
1 = Interrupt required after the buffer is sent.
Ownership of the transfer buffer (set by the host CPU and cleared by the CD2231)
0 = Buffer not ready to be used by CD2231.
1 = Buffer is ready for CD2231 to transmit.
EOB
Bit 5
Bit 4
0
Append
Bit 3
Bit 2
0
Motorola Hex Address: x’5E
INTR
Bit 1
Intel Hex Address: x’5D
2231own
Bit 0
151