CD2231 Intel Corporation, CD2231 Datasheet - Page 20

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
4.0
4.1
4.1.1
4.1.2
20
GFRCR
CAR
CMR
COR1
COR2
COR3
COR4
COR5
Name
Name
Global Firmware Revision Code Register
Channel Mode Register
Channel Option Register 1
Channel Option Register 2
Channel Option Register 3
Channel Option Register 4
Channel Option Register 5
Channel Access Register
Register Table
Registers in the CD2231 are either Global or Per-Channel. The column ‘Address mode’ in the
memory map on the following pages defines this attribute for each register. Only one set of Global
registers exists, and are accessible by the host at any time. Two sets of Per-Channel registers exist,
and the set accessible at any one time is determined by the currently active channel number. The
channel number is selected by the host in normal (non-interrupt) processing by writing to the
Channel Access register. The channel number in the Channel Access register remains in force until
changed by the host. The channel number is provided automatically by the CD2231 during
interrupt service routines and DMA transfers.
In the following list, some register locations appear twice. They have different names and functions
for asynchronous and synchronous protocol operations. See
datasheet for detailed descriptions of all register functions.
Memory Map
Global Registers
The following notes are applicable for
NOTES:
Option Registers
1. Address mode G: Global register — one set is always accessible.
2. INT = address for Intel -style processor.
3. MOT = address for Motorola -style processor.
Address mode P: Per-Channel register — two sets, one per channel, accessible by CAR or
interrupt context.
Description
Description
Mode
Addr.
Section 4.1.1
Mode
Addr.
P
P
P
P
P
P
G
G
1
1
INT
18
13
14
15
16
17
INT
EC
82
2
through
2
MOT
Chapter 8.0 on page 88
1B
10
17
16
15
14
MOT
Section
EE
81
3
3
4.1.8.
Size
B
B
B
B
B
B
Size
B
B
Access
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
of this
Datasheet
Page
Page
89
90
92
94
98
99
88
88