CD2231 Intel Corporation, CD2231 Datasheet - Page 50

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
50
Figure 8. Receiver A and B Buffers
NOTE: Number of bits in each register is shown in parentheses ( ).
size of the gap supplied by the host is sufficient to fill or complete the current buffer, the CD2231
automatically switches to the other buffer and advances the Receive Current Buffer Address
enough to complete the desired gap. The CD2231 readjusts data alignment in its internal FIFO as
needed to maintain alignment with the external buffer.
Receiver A and B Buffers
In
(DMABSTS, ARBADR, ARBCNT, ARBSTS, RCBADR, BRBADR, BRBCNT, and BRBSTS)
are inside the CD2231.
Example 1
Receive a frame from channel 1, no chaining.
1. The host must first make a receive buffer available before a frame can be received. Thus, the
2. The host sets up the starting address — ARBADR, and the buffer byte count — ARBCNT.
3. The host then gives the buffer to the CD2231 by setting the 2231own bit in the status register
4. The Rbusy bit (DMABSTS[0]) for channel 1 is ‘0’ until a frame starts to be received. When
5. At the end of the received frame, the CD2231 tests for correct end of frame delimiter and
Figure
host checks the Nrbuf bit in the DMABSTS register for channel 1 to determine which buffer is
next. In this example, Nrbuf is set to ‘0’, indicating that Buffer A is used next.
When the host writes the count — ARBCNT, the host has defined the size limit for the buffer.
— ARBSTS. This notifies the CD2231 that it is now alright to write received.
frame data starts coming in, the CD2231 sets Rbusy to notify the host that Buffer B is next. As
data bytes are written into the buffer, the current buffer pointer, RCBADR, is updated by the
CD2231.
CRC. When the received frame is complete, the CD2231 clears the Rbusy bit. In this example,
there is no receive chaining, so the received frame byte count is less than or equal to the buffer
CD2231 Transmit
Buffer A and Buffer B do not need to be the same length.
DMA Registers
(Currently using Buffer A)
ARBADR (32)
RCBADR (32)
BRBADR (32)
ARBCNT (16)
BRBCNT (16)
ARBSTS (8)
BRBSTS (8)
(Status register)
(Status register)
8, buffers A and B are contained in RAM external to the CD2231. All others
Starting Address
Starting Address
Buffer Byte Count
Current Address
Buffer Byte Count
Physical
Memory
Receiver
Receiver
Buffer
Buffer
A
B
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