CD2231 Intel Corporation, CD2231 Datasheet - Page 92

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.2.3
8.2.3.1
8.2.3.2
92
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Register Name: COR2
Register Description: Channel Option Register 2
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 7
IXM
0
Channel Option Register 2 (COR2)
COR2 — HDLC Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Asynchronous / Async-HDLC / PPP Mode
Bit 7
FCSApd
TxIBE
Bit 6
Bit 6
Reserved – must be ‘0’.
FCS append
0 = Receive CRC is not passed to the host at end of frame
1 = Receive CRC is passed to the host at end of frame
Reserved – must be ‘0’.
CRCNinv
0 = CRC is transmitted inverted (that is, CRC V.41)
1 = CRC is not transmitted inverted (that is, CRC-16)
Reserved – must be ‘0’.
RTS automatic output enable
When set, if the channel is enabled, the CD2231 automatically asserts the RTS* out-
put when it has characters to send. When Idle-in Mark mode is selected, RTS* is
asserted prior to opening flags and remains asserted until after a closing flag has been
transmitted.
CTS automatic enable
Enables CTS* input to be used as the automatic transmitter enable/disable. If
enabled, the CTS input is checked before frame transmission starts.
DSR Automatic Enable
Enable the DSR* input as the automatic receiver enable/disable. If enabled, DSR*
is checked at the beginning of each received frame.
IXM – Implied XON mode
IXM has meaning only when TxIBE is set.
If transmission has been stopped due to a received XOFF character, and:
Bit 5
Bit 5
0
0
CRCNinv
Bit 4
Bit 4
0
Bit 3
RLM
Bit 3
0
RtsAO
RtsAO
Bit 2
Bit 2
Motorola Hex Address: x’17
Motorola Hex Address: x’17
CtsAE
CtsAE
Bit 1
Bit 1
Intel Hex Address: x’14
Intel Hex Address: x’14
Datasheet
DsrAE
DsrAE
Bit 0
Bit 0

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