CD2231 Intel Corporation, CD2231 Datasheet - Page 114

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.4.1.2
114
Register Name: CCR
Register Description: Channel Command, Mode 2
Default Value: x’00
Access: Byte Read/Write
Warning:
Bit 7
1
If the Initialize Channel command is issued after a channel is already in operation, then a Clear
Channel command must be issued prior to, or coinciding with, the Initialize Channel command.
Failure to observe this requirement will result in unpredictable device behavior.
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCR Mode 2
Either one or both of the timers can be cleared with a single command. Note that if the running
timer value is 01h at the time this command is issued, the timer may expire and cause a timer
interrupt before the command is processed.
Bit 7
Bit 6
Bit 5
Bit 4
ClrT1
Bit 6
RESET ALL
An on-chip firmware initialization of all channels is performed. All channel and glo-
bal parameters are reset to their power-on reset condition. This command is the
strongest the host can issue. None of the other command bits are interpreted if the
RESET ALL command is given. The host must re-initialize the CD2231 following
the execution of this command just as after a hardware power-on reset. When this
command is completed, the GFRCR is updated with the firmware revision code.
Enable transmitter
Enables the transmitter by setting TxEn bit in the Channel Status register (CSR[3]).
In Asynchronous mode, this command also clears the transmit flow control options.
Disable transmitter
Disables the transmitter by clearing TxEn bit (CSR[3]). In Asynchronous mode, the
Transmit Flow Control bits are cleared.
Enable receiver
Enables the receiver by setting the RxEn bit (CSR[7]). In Asynchronous mode, the
Receive Flow Control bits are cleared.
Disable receiver
Disables the receiver by clearing the RxEn bit (CSR[7]). In Asynchronous mode, the
Receive Flow Control bits are cleared.
Must be ‘1’.
Clear timer 1
General timer 1 is cleared.
Clear timer 2
General timer 2 is cleared.
Clear receiver command
This command only affects the receiver. It resets all receiver functions like a combi-
nation of clear channel, initialize channel and enable receiver commands. ClrRcv
clears the receive FIFO and clears receive status in the CSR, except for the RcvEn
bit. ClrRcv clears receive DMA buffer status in ARBSTS, BRBSTS, and Receive
Status bits in DMABSTS. Clearing the 2231own bits in both the Receive Buffer Sta-
tus registers means that DMA buffers have to be returned to the CD2231 before
receive transfers begin again.
ClrT2
Bit 5
ClrRcv
Bit 4
ClrTx
Bit 3
Bit 2
0
Motorola Hex Address: x’13
Bit 1
0
Intel Hex Address: x’10
Datasheet
Bit 0
0