CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
Page 111
112
Page 112
113
Page 113
114
Page 114
115
Page 115
116
Page 116
117
Page 117
118
Page 118
119
Page 119
120
Page 120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Page 115/178

Download datasheet (3Mb)Embed
PrevNext
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
For Synchronous modes, this command puts the receiver back into Syn/Flag Hunt
mode.
Bit 3
Clear transmitter command
This command only affects the trasmitter and is only available on Revision C and
later devices and is only effective in asynchronous protocols. It resets all transmitter
functions like a combination of clear channel, initialize channel and transmit com-
mands. ClrTx clears the transmit FIFO and clears transmit status in the CSR, except
for the TxEn bit. ClrTx clears transmit DMA buffer status in ATBSTS, BTBSTS,
and Transmit Status bits in DMABSTS. Clearing the 24312OWN bits in both the
Transmit Buffer Status registers means that DMA buffers have to be returned to the
CD2231 before transmit transfers begin again.
Bits 2:0
Reserved – must be ‘0’.
8.4.2
Special Transmit Command Register (STCR)
8.4.2.1
Async-HDLC/PPP Mode
Register Name: STCR
Register Description: Special Transmit Command
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
AbortTx
0
Special characters can be transmitted preemptively (ahead of any characters in the transmit FIFO)
upon commands described below. When the special character is transmitted, the STCR is cleared
by the device.
Bit 7
Reserved – must be ‘0’.
Bit 6
Abort
Transmission of the two-character sequence (7D–7E) aborts the current transmit
frame. All data in the FIFO following the abort is discarded. If DMA is used, the
remaining data up to the EOF is discarded.
Bits 5:4
Reserved – must be ‘0’.
Bit 3
SndSpc – Send special character command
When clear, the frame, Xon, and Xoff bits described below have no meaning.
When set, the host should also set one of the following bits: frame, Xon, or Xoff.
Bit 2
Frame – Send framing error
Causes the next character in the transmit stream to be sent with an incorrect Stop bit
(Stop bit is ‘0’).
This bit is intended as a test function. Unlike the Abort bit, this bit does not terminate
the transmission.
Bit 1
Xon – Send XON
Causes the transmission of an XON (cntl-Q or hex 11).
Note: The user should not use the send XON/XOFF commands if automatic in-band flow control is
enabled (Asynchronous modes only) in COR5.
Datasheet
Bit 4
Bit 3
Bit 2
0
SndSpc
Frame
Intel Hex Address: x’11
Motorola Hex Address: x’12
Bit 1
Bit 0
Xon
Xoff
115