CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
8.4.2.3
Async and HDLC Modes
Register Name: STCR
Register Description: Special Transmitl Command
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
AbortTx
AppdCmp
The CD2231 clears the register to zero when it accepts a host CPU command.
Bit 7
Reserved – must be ‘0’.
Bit 6
Abort transmission (HDLC)
Terminates the frame currently in transmission with an abort sequence. In DMA
mode, all data up to the next EOF is discarded.
Bit 5
Append complete (Asynchronous DMA mode)
This bit should be set by the host when the last addition has been made to the append
buffer.
Bit 4
Reserved – must be ‘0’.
Bit 3
SndSpc – Send special character command
In Asynchronous mode, sends a user-defined special character or special-character
sequence. The special character is transmitted ahead of any data remaining in the
FIFO.
Bits 2:0
Special character select
NOTE: The user should not use the send XON/XOFF commands if automatic in-band flow control is enabled
(Asynchronous modes only) in COR5.
8.4.3
Channel Status Register (CSR)
This status register stores the current state of the channel. It can be read by the host at any time. The
states of the RxEn and the TxEn bits are controlled by host CPU commands to the CCR.
Datasheet
Bit 4
Bit 3
0
SndSpc
SSPC2
SSCP1
SSPC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Intel Hex Address: x’11
Motorola Hex Address: x’12
Bit 2
Bit 1
Bit 0
SSPC2
SSPC1
SSPC0
Function
Reserved
Send Special Character 1
Send Special Character 2
Send Special Character 3
Send Special Character 4
Reserved
Reserved
Reserved
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