CD2231 Intel Corporation, CD2231 Datasheet - Page 117

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

8.4.2.3
8.4.3
Datasheet
Register Name: STCR
Register Description: Special Transmitl Command
Default Value: x’00
Access: Byte Read/Write
Bit 7
0
Async and HDLC Modes
The CD2231 clears the register to zero when it accepts a host CPU command.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2:0
NOTE: The user should not use the send XON/XOFF commands if automatic in-band flow control is enabled
Channel Status Register (CSR)
This status register stores the current state of the channel. It can be read by the host at any time. The
states of the RxEn and the TxEn bits are controlled by host CPU commands to the CCR.
AbortTx
Bit 6
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
(Asynchronous modes only) in COR5.
AppdCmp
Reserved – must be ‘0’.
Abort transmission (HDLC)
Terminates the frame currently in transmission with an abort sequence. In DMA
mode, all data up to the next EOF is discarded.
Append complete (Asynchronous DMA mode)
This bit should be set by the host when the last addition has been made to the append
buffer.
Reserved – must be ‘0’.
SndSpc – Send special character command
In Asynchronous mode, sends a user-defined special character or special-character
sequence. The special character is transmitted ahead of any data remaining in the
FIFO.
Special character select
Bit 5
SSPC2
0
0
0
0
1
1
1
1
Bit 4
0
SSCP1
0
0
1
1
0
0
1
1
SndSpc
Bit 3
SSPC0
0
1
0
1
0
1
0
1
SSPC2
Reserved
Send Special Character 1
Send Special Character 2
Send Special Character 3
Send Special Character 4
Reserved
Reserved
Reserved
Bit 2
Motorola Hex Address: x’12
SSPC1
Function
Bit 1
Intel Hex Address: x’11
SSPC0
Bit 0
117