CD2231 Intel Corporation, CD2231 Datasheet - Page 122

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Note: If the transmit clock source is a 1 clock on the TXCIN pin, this signal cannot be driven on
TXCOUT/DTR*.
Bit 3
Reserved – must be ‘0’.
Bit 2
Reserved – returns ‘0’ when read; writing has no effect
Bit 1
DTR – Current state of data terminal ready output
Bit 0
RTS – Current state of request to send output
8.5
Interrupt Registers
8.5.1
General Interrupt Registers
8.5.1.1
Local Interrupt Vector Register (LIVR)
Register Name: LIVR
Register Description: Local Interrupt Vector
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
X
X
X
The host effectively controls bits 7:2; the device provides bits 1 and 0 within an interrupt
acknowledge context.
The CD2231 has one Local Interrupt Vector register per channel, each with six host-defined bits.
The host can opt to embed the channel number and the protocol in use on the channel in the
channel vector. The CD2231 supplies two modified bits signifying the type of interrupt service
required.
Bits 7:2
User-defined. These six bits can be used as the CD2231 device ID number.
Bits 1:0
Interrupt type. These two bits indicate the group/type of interrupt occurring.
IT[1:0]
Note: Note that because the CD2231 provides a unique Local Interrupt Vector register for each channel,
the host has the option to include the channel number within the interrupt vector.
122
Bit 4
Bit 3
X
X
Group/Type
Group 1: Modem signal change interrupt/general
01
timer interrupt
10
Group 2: Transmit data interrupt
11
Group 3: Receive data interrupt
00
Group 3: Receive exception interrupt
Intel Hex Address: x’0A
Motorola Hex Address: x’09
Bit 2
Bit 1
Bit 0
X
IT1
IT0
Datasheet

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