CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Bit 7
Modem pin change detect
Master interrupt enable for modem change detect functions. The host can select
which modem pins are watched for input change and select either or both directions
of change by programming the change detect option bits in COR4 and COR5. A
Group1 type interrupt (see LIVR description) is generated from this enable.
Bits 6:4
Reserved – must be ‘0’.
Bit 3
Rx data
The receive FIFO threshold has been reached in Interrupt Transfer mode, causing a
Group 3 receive data interrupt. Any receive exception causes a Group 3 receive
exception interrupt.
Bit 2
Timer
General timer(s) timeout
In Synchronous mode, this bit enables a Group 1 interrupt when either timer reaches
zero.
Bit 1
Tx Mpty
Transmitter empty. If enabled, a Group 2 interrupt is generated when the channel is
completely empty of transmit data.
Bit 0
Tx Data
Any transmit exception or transmit FIFO threshold reached in Interrupt Transfer
mode. Group 2 interrupts are generated at the end of transmit DMA buffers or when
the FIFO threshold is reached in Interrupt Transfer mode.
8.5.1.4
Local Interrupting Channel Register (LICR)
Register Name: LICR
Register Description: Local Interrupting Channel
Default Value: C1:C0 contain channel number
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
X
X
X
These per-channel registers are initialized with each channel number. The locations are RAM
registers and can be used for any purpose.
Bits 7:4
User-defined
Bits 3:2
Defines the interrupting channel number
Bits 1:0
User-defined
124
Bit 4
Bit 3
X
X
C0
Channel Number
0
Channel 0
1
Channel 1
Intel Hex Address: x’25
Motorola Hex Address: x’26
Bit 2
Bit 1
Bit 0
C0
X
X
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