CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
8.5.1.5
Interrupt Stack Register (STK)
Register Name: STK
Register Description: Interrupt Stack
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 6
Bit 5
CLvl [1]
MLvl [1]
TLvl [1]
This register is a 4-bit-deep by 2-bit-wide stack that contains the internal interrupt nesting history.
The stack is pushed from bits 7 and 0 toward the center during an interrupt acknowledge cycle, and
popped from the center during a write to an end of interrupt register.
Bits 7, 0
CLvl [0:1]These bits provide the currently active interrupt level.
CLvl [1]
Bits 6, 1
MLvl [0:1]These bits hold a previously active interrupt now nested.
Bits 5, 2
TLvl [0:1]These bits hold the oldest interrupt now nested two bits deep.
Bits 4:3
Reserved – always returns ‘0’ when read.
8.5.2
Receive Interrupt Registers
8.5.2.1
Receive Priority Interrupt Level Register (RPILR)
Register Name: RPILR
Register Description: Receive Priority Interrupt Match
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2231 interrupt types (modem, transmit, or
receive) is being acknowledged when IACKIN* is asserted. The CD2231 compares bits 0–6 in this
register with A[0–6] to determine if the acknowledge level is correct. The value programmed in the
MSB of the register has no effect on the IACK cycle.
RPILR must contain the code used to acknowledge receive interrupts.
Datasheet
Bit 4
Bit 3
0
0
CLvl [0]
0
0
No interrupt active; CAR provides the current channel number
Currently in a modem interrupt service, MIR provides the
0
1
current channel number.
Currently in a transmit interrupt service, TIR provides the
1
0
current channel number.
1
1
Currently in a receive interrupt service, RIR provides the
current channel number.
Bit 4
Bit 3
User-assigned priority match value
Intel Hex Address: x’E0
Motorola Hex Address: x’E2
Bit 2
Bit 1
Bit 0
TLvl [0]
MLvl [0]
CLvl [0]
Intel Hex Address: x’E3
Motorola Hex Address: x’E1
Bit 2
Bit 1
Bit 0
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