CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Note: Bit 7 of the register is always read back as ‘0’. When each of the three Priority Interrupt Level
registers is programmed with the same value, they are internally prioritized, with receive as the
highest priority, followed by transmit and modem.
8.5.2.2
Receive Interrupt Register (RIR)
Register Name: RIR
Register Description: Receive Interrupt
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Ren
Ract
Reoi
Bit 7
Ren
Receive enable is set by the CD2231 to initiate a receive interrupt request sequence.
It is cleared during a valid receive interrupt acknowledge cycle.
Bit 6
Ract
Receive active is set automatically when Ren is set, and the Fair Share logic allows
the assertion of a receive interrupt request. It is cleared when the host CPU writes to
the Receive End of Interrupt register.
Bit 5
Reoi
Receive end of interrupt is set automatically when the host CPU writes to the
Receive End of Interrupt register while in a receive interrupt routine.
Bit 4
Reserved – always returns ‘0’ when read.
Bits 3:2
Rvct [1:0]
Receive vector bits are set by the CD2231 to provide the lower two bits of the vector
supplied to the host CPU during an interrupt acknowledge cycle. Receive good data
vector is decoded as follows: Rvct [1] = 1, and Rvct [0] = 1. Receive exception vec-
tor is decoded as follows: Rvct [1] = 0, and Rvct [0] = 0.
Bit 1
Reserved – always returns ‘0’ when read.
Bit 0
Rcn [0]
Receive channel number is set by the CD2231 to indicate the channel requiring
receive interrupt service.
126
Bit 4
Bit 3
0
Rvct [1]
Ren
Ract
Reoi
0
0
0
1
0
0
1
1
0
0
1
0
0
0
1
Intel Hex Address: x’EF
Motorola Hex Address: x’ED
Bit 2
Bit 1
Bit 0
Rvct [0]
0
Rcn [0]
Sequence of Events
Idle
Receive interrupt requested, but not
asserted
Receive interrupt asserted
Receive interrupt acknowledged
Receive interrupt service routine completed
Datasheet