CD2231 Intel Corporation, CD2231 Datasheet - Page 127

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

8.5.2.3
Datasheet
Register Name: RISR
Register Description: Receive Interrupt Status
Default Value: x’00
Access: Word Read Only
Register Name: RISRl
Register Description: Receive Interrupt Status — Low
Default Value: x’00
Access: Byte Read only
Bit 15
Bit 7
Bit 7
0
Receive Interrupt Status Register (RISR
This register reports the status of the channel during the receive interrupt service. It is a 16-bit
register, with the lower byte displaying current receive character-oriented status while the upper
byte displays current DMA interrupt status. The upper byte is not used if DMA mode is not active.
RISRl — HDLC Mode
If RxData in IER is set, these interrupts are enabled.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the Receive End of Interrupt register. The host can load only one of the two timers in the
interrupt service routine.
Bit 14
Bit 6
Bit 6
EOF
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Reserved, always returns ‘0’ when read.
Receiving a data frame is essentially complete.
Received abort sequence terminating the frame.
CRC error on current frame.
Overrun error – indicates that new data has arrived, but the CD2231 FIFO or holding
registers are full. The new data is lost, and the overrun indication is flagged on the
last character received before the overrun occurred. In HDLC and Bisync modes, the
remainder of a frame, following an overrun, is discarded.
Residual indication – indicates that the last character of the frame was a partial char-
acter.
Reserved, always returns ‘0’ when read.
Clear detect – indicates an X.21 data transfer phase clear signal has been detected.
This is defined as two consecutive all-zero receive characters with the CTS* pin
high. Clear Detect mode is enabled by COR1.
RxAbt
Bit 13
Bit 5
Bit 5
Bit 12
CRC
Bit 4
Bit 4
RISR High
RISR Low
Bit 11
Bit 3
Bit 3
OE
Reslnd
Bit 10
Bit 2
Bit 2
Motorola Hex Address: x’88
Motorola Hex Address: x’89
Bit 9
Bit 1
Bit 1
0
Intel Hex Address: x’8A
Intel Hex Address: x’8A
ClrDct
Bit 8
Bit 0
Bit 0
127