CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Bit 5
RxAbt – Receive abort
The rxabt bit indicates that an abort sequence (7D–7E) has been received.
Bit 4
Unused; returns ‘0’ when read.
Bit 3
OE – Overrun error
The OE bit indicates that the receiver buffer and FIFO have been overrun. At least
one new character has been received, but lost since there was no room available in
the receiver buffer and/or FIFO.
Bit 2
FE – Framing error
The FE bit indicates that a character has been received with an incorrect Stop bit. The
Stop bit was ‘0’; it should have been ‘1’.
Bit 1
Reserved – always returns ‘0’ when read.
Bit 0
Break – Break detection
The Break bit indicates that a break has been received. A break is a continuous
sequence of at least ten ‘0’ bits.
Note: 0E, FE, and break are cumulative over the entire packet in PPP mode. This means that the
respective error occurred somewhere in the packet, but did not cause an immediate interrupt.
8.5.2.4
Receive Interrupt Status Register high (RISRh)
Register Name: RISRh
Register Description: Receive Interrupt Status — High
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Berr
EOF
EOB
This register is used in DMA mode only.
Bit 7
Bus error (written by CD2231)
0 = No bus error
1 = Bus error was detected on the last transfer
The actual address at which the error occurred is available in the Receive Current
Buffer Address register. In response to a bus error status, the host has two possible
options:
1. Retry from the next position in the buffer.
2. Terminate this buffer by setting TermBuff bit in REOIR, and move onto the next.
Bit 6
Reception of a data frame is complete (Sync DMA mode only).
Bit 5
The end of a receive buffer has been reached. Used only for DMA-supported trans-
mission. The end of one of the host-supplied receive buffers has been reached.
Bit 4
Unused; returns ‘0’ when read.
Bit 3
Status during buffer A or buffer B data transfer
0 = Buffer A
1 = Buffer B
Bits 2:0
Unused; returns ‘0’ when read.
130
Bit 4
Bit 3
Bit 2
0
BA/BB
0
Intel Hex Address: x’8B
Motorola Hex Address: x’88
Bit 1
Bit 0
0
0
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