CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
to the other buffer. This bit should only be set in response to an async exception
interrupt. If the buffer is terminated in response to an exception character (that is,
parity error) interrupt and the discard exception character bit is not set, the exception
character is written at the start of the next buffer.
Before writing the terminate buffer command to REOIR, a new buffer descriptor can
be written to the current buffer.
Bit 6
Discard exception character (DMA mode only)
When this bit is set in response to an async exception interrupt, the exception char-
acter is not transferred to memory.
Bit 5
Set general timer 2 in Synchronous modes
0 = do not set general timer
1 = load the value, to general timer 2, provided in RISRl.
Bit 4
Set general timer 1 in Synchronous modes
0 = do not set general timer 1
1 = load the value, to the high byte of general timer 1, provided in RISRl.
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in the Receive Interrupt Status register. When the timer reaches ‘0’, the
CD2231 generates a modem/timer group interrupt to the host.
Bit 3
No transfer of data
This bit must be set by the host, if no data is transferred from the receive FIFO during
a receive interrupt.
Bits 2:0
Gap2, Gap1, Gap0
Size of the optional gaps to be left in DMA buffer, starting at the current location,
before resuming data transfer. The CD2231 moves forward its buffer address pointer
to the selected number of bytes. It does not write to any location ‘in the gap’. If the
gap is large enough to complete, or extend beyond the end of the current buffer, it is
completed, and the gap continued in the other receive buffer. If the discard exception
character is not selected, the character where the exception occurred is written to the
buffer following the gap.
REOIR — Async-HDLC / PPP / SLIP / MNP 4 Mode
Register Name: REOIR
Register Description: Receive End of Interrupt
Default Value: x’00
Access: Byte Write Only
Bit 7
Bit 6
Bit 5
TermBuff
DiscExc
SetTm2
The CD2231 interprets values written to this register at the completion of all receive interrupts.
Bit 7
Terminate current DMA buffer
If this bit is set, the current receive buffer is terminated and data transfer is switched
to the other buffer. This bit should only be set in response to an async exception
interrupt. If the buffer is terminated in response to an exception character (that is,
parity error) interrupt and the discard exception character bit is not set, the exception
character is written at the start of the next buffer.
Before writing the terminate buffer command to REOIR, a new buffer descriptor can
be written to the current buffer.
132
Bit 4
Bit 3
Bit 2
SetTm1
NoTrans
0
Intel Hex Address: x’87
Motorola Hex Address: x’84
Bit 1
Bit 0
0
0
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