CD2231 Intel Corporation, CD2231 Datasheet - Page 133

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

8.5.3
8.5.3.1
Datasheet
Register Name: TPILR
Register Description: Transmit Priority Interrupt Match
Default Value: x’00
Access: Byte Read/Write
Bit 7
Note: Bit 7 of this register is always read back as ‘0’. When each of the three Priority Interrupt Level
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2:0
Transmit Interrupt Registers
Transmit Priority Interrupt Level Register (TPILR)
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2231 interrupt types (modem, transmit, or
receive) is being acknowledged when IACKIN* is asserted. The CD2231 compares bits 0–6 in this
register with A[0–6] to determine if the acknowledge level is correct. The value programmed in the
MSB of the register has no effect on the IACK cycle.
The TPILR must contain the code used to acknowledge transmit interrupts.
registers are programmed with the same value, they are internally prioritized, with receive as the
highest priority, followed by transmit and modem.
Bit 6
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Discard exception character (DMA mode only)
When this bit is set in response to an async exception interrupt, the exception char-
acter is not transferred to memory.
Set general timer 2 in Synchronous modes
0 = do not set general timer
1 = load the value, to general timer 2, provided in RISRl.
Set general timer 1 in Synchronous modes
0 = do not set general timer 1
1 = load the value, to the high byte of general timer 1, provided in RISRl.
At the end of an interrupt service routine, the user can set a timer by setting a timer
value in the Receive Interrupt Status register. When the timer reaches ‘0’, the
CD2231 generates a modem/timer group interrupt to the host.
No transfer of data
This bit must be set by the host, if no data is transferred from the receive FIFO during
a receive interrupt.
Not used; must be zero.
Bit 5
User-assigned priority match value
Bit 4
Bit 3
Bit 2
Motorola Hex Address: x’E0
Bit 1
Intel Hex Address: x’E2
Bit 0
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