CD2231 Intel Corporation, CD2231 Datasheet - Page 134

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.5.3.2
Transmit Interrupt Register (TIR)
Register Name: TIR
Register Description: Transmit Interrupt
Default Value: None, value varies
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Ten
Tact
Teoi
Bit 7
Ten
Transmit enable is set by the CD2231 to initiate a transmit interrupt request
sequence. It is cleared during a valid transmit interrupt acknowledge cycle.
Bit 6
Tact
Transmit active is set automatically when Ten is set, and the Fair Share logic allows
the assertion of a transmit interrupt request. It is cleared when the host CPU writes
to the Transmit End of Interrupt register.
Bit 5
Teoi
Transmit end of interrupt is set automatically when the host CPU writes to the Trans-
mit End of Interrupt register while in a transmit interrupt routine.
Bit 4
Reserved – always returns ‘0’ when read.
Bits 3:2
Tvct [1:0]
Transmit Vector bits are set by the CD2231 to provide the lower two bits of the vec-
tor supplied to the host CPU during an interrupt acknowledge cycle. Transmit vector
is decoded as follows: Tvct [1] = 1, and Tvct [0] = 0.
Bit 1
Reserved – always returns ‘0’ when read.
Bit 0
Tcn [0]
Transmit channel number is set by the CD2231 to indicate the channel requiring
transmit interrupt service.
134
Bit 4
Bit 3
0
Tvct [1]
Ten
Tact
Teoi
Sequence of Events
0
0
0
Idle
1
0
0
Transmit interrupt requested, but not asserted
1
1
0
Transmit interrupt asserted
0
1
0
Transmit interrupt acknowledged
0
0
1
Transmit interrupt service routine completed
Intel Hex Address: x’EE
Motorola Hex Address: x’EC
Bit 2
Bit 1
Bit 0
Tvct [0]
0
Tcn [0]
Datasheet

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