CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
8.5.3.3
Transmit Interrupt Status Register (TISR)
Register Name: TISR
Register Description: Transmit Interrupt Status
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 6
Bit 5
Berr
EOF
EOB
When the host receives a transmit interrupt, the following status is provided in this register:
Bit 7
Berr – Bus error (written by the CD2231)
0 = no bus error
1 = bus error was detected on the last transfer
Bit 6
EOF – Transmit end of frame indication in the DMA mode
This interrupt occurs when the final data character of a transmit frame is transferred
to the transmit FIFO.
Bit 5
EOB – Transmit end of buffer indication in the DMA mode
Bit 4
Transmit underrun error (HDLC only), otherwise zero (Async, PPP, SLIP, and
MNP4).
Bit 3
BA/BB – Applicable buffer for the register interrupt
0 = Transmit Buffer A
1 = Transmit Buffer B
Bit 2
Reserved – always returns ‘0’ when read.
Bit 1
TxEmpty – Transmitter empty
All characters have been completely transmitted, and the serial output is idle.
Bit 0
TxDat – The number of characters in the FIFO is below the threshold.
8.5.3.4
Transmit FIFO Transfer Count (TFTC)
Register Name: TFTC
Register Description: Transmit FIFO Transfer Count
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 6
Bit 5
0
0
0
Bits 7:5
Reserved – always returns ‘0’ when read.
Bits 4:0
Transmit data count
If the Transmit channel is interrupt driven, a non-zero value is a request for data.
These bits give the number of spaces available in the transmit FIFO.
Datasheet
Bit 4
Bit 3
Bit 2
UE
BA/BB
0
Bit 4
Bit 3
Bit 2
TxCt4
TxCt3
TxCt2
Intel Hex Address: x’89
Motorola Hex Address: x’8A
Bit 1
Bit 0
TxEmpty
TxDat
Intel Hex Address: x’83
Motorola Hex Address: x’80
Bit 1
Bit 0
TxCt1
TxCt0
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