CD2231 Intel Corporation, CD2231 Datasheet - Page 135

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

8.5.3.3
8.5.3.4
Datasheet
Register Name: TISR
Register Description: Transmit Interrupt Status
Default Value: x’00
Access: Byte Read only
Register Name: TFTC
Register Description: Transmit FIFO Transfer Count
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 7
Berr
0
Transmit Interrupt Status Register (TISR)
When the host receives a transmit interrupt, the following status is provided in this register:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Transmit FIFO Transfer Count (TFTC)
Bits 7:5
Bits 4:0
EOF
Bit 6
Bit 6
0
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
Berr – Bus error (written by the CD2231)
0 = no bus error
1 = bus error was detected on the last transfer
EOF – Transmit end of frame indication in the DMA mode
This interrupt occurs when the final data character of a transmit frame is transferred
to the transmit FIFO.
EOB – Transmit end of buffer indication in the DMA mode
Transmit underrun error (HDLC only), otherwise zero (Async, PPP, SLIP, and
MNP4).
BA/BB – Applicable buffer for the register interrupt
0 = Transmit Buffer A
1 = Transmit Buffer B
Reserved – always returns ‘0’ when read.
TxEmpty – Transmitter empty
All characters have been completely transmitted, and the serial output is idle.
TxDat – The number of characters in the FIFO is below the threshold.
Reserved – always returns ‘0’ when read.
Transmit data count
If the Transmit channel is interrupt driven, a non-zero value is a request for data.
These bits give the number of spaces available in the transmit FIFO.
EOB
Bit 5
Bit 5
0
TxCt4
Bit 4
Bit 4
UE
BA/BB
TxCt3
Bit 3
Bit 3
TxCt2
Bit 2
Bit 2
0
Motorola Hex Address: x’8A
TxEmpty
Motorola Hex Address: x’80
TxCt1
Bit 1
Bit 1
Intel Hex Address: x’89
Intel Hex Address: x’83
TxDat
TxCt0
Bit 0
Bit 0
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