CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
0 = Append buffer is not in use.
1 = Append buffer is in use.
Bit 3
Ntbuf
Next transmit buffer
0 = Buffer A is the next transmit buffer.
1 = Buffer B is the next transmit buffer.
This bit is toggled when transmission starts from a buffer, that is, when data is first
read from Buffer A, the bit is set to indicate that Buffer B is next.
Bit 2
Tbusy
Current transmit buffer is in use
0 = No buffer is in use.
1 = Current transmit buffer is in use.
Bit 1
Nrbuf
Next receive buffer
0 = Buffer A is the next receive buffer.
1 = Buffer B is the next receive buffer.
This bit is toggled when receive data is first written to a buffer, that is, when data is
first written to Buffer A, the bit is set to indicate Buffer B is next.
Bit 0
Rbusy
Current receive buffer is in use
0 = No buffer is in use.
1 = Current receive buffer is in use.
8.6.4
DMA Receive Registers
8.6.4.1
A Receive Buffer Address Register — Lower (ARBADRL)
Register Name: ARBADRL
Register Description: Receive Buffer ‘A’ 32-bit Address, lower word
Default Value: x’0000
Access: Word Read/Write
Bit 15
Bit 14
Bit 13
Bit 7
Bit 6
Bit 5
Datasheet
Bit 12
Bit 11
Binary address value, 32-bit address, bits 15:8
Bit 4
Bit 3
Binary address value, 32-bit address, bits 7:0
Intel Hex Address: x’40
Motorola Hex Address: x’42
Bit 10
Bit 9
Bit 8
Bit 2
Bit 1
Bit 0
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