CD2231 Intel Corporation, CD2231 Datasheet - Page 141

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
8.6.4
8.6.4.1
Datasheet
Register Name: ARBADRL
Register Description: Receive Buffer ‘A’ 32-bit Address, lower word
Default Value: x’0000
Access: Word Read/Write
Bit 15
Bit 7
Bit 3
Bit 2
Bit 1
Bit 0
DMA Receive Registers
A Receive Buffer Address Register — Lower (ARBADRL)
Bit 14
Bit 6
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
0 = Append buffer is not in use.
1 = Append buffer is in use.
Ntbuf
Next transmit buffer
0 = Buffer A is the next transmit buffer.
1 = Buffer B is the next transmit buffer.
This bit is toggled when transmission starts from a buffer, that is, when data is first
read from Buffer A, the bit is set to indicate that Buffer B is next.
Tbusy
Current transmit buffer is in use
0 = No buffer is in use.
1 = Current transmit buffer is in use.
Nrbuf
Next receive buffer
0 = Buffer A is the next receive buffer.
1 = Buffer B is the next receive buffer.
This bit is toggled when receive data is first written to a buffer, that is, when data is
first written to Buffer A, the bit is set to indicate Buffer B is next.
Rbusy
Current receive buffer is in use
0 = No buffer is in use.
1 = Current receive buffer is in use.
Bit 13
Bit 5
Binary address value, 32-bit address, bits 15:8
Binary address value, 32-bit address, bits 7:0
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Motorola Hex Address: x’42
Bit 9
Bit 1
Intel Hex Address: x’40
Bit 8
Bit 0
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