CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
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F
Fair Share scheme 40
FCS (frame check sequence) 67
FCS mode 96
FCT (flow control transparency) mode 98, 103
fields, A and C 69
FIFO and timer operations 41
Flag Hunt mode 68
Flag mode 67, 68
format
character 69
frame 69
frame format 69
functional description 34
G
global initialization 85
H
hardware configurations
32-bit data bus 65
DMA connections 65
DTE and DCE interface 65
hardware signals and IACK cycles 39
HDLC DMA channel setup examples 86
HDLC mode 90, 92, 96, 118, 127
HDLC processing 67
High-Impedance mode 18
host interface 34
host read and write cycles 34
host read cycle 35
host read/write 157
host write cycle 36
I
Idle mode 96
Idle-in Mark mode 96
initialization sequence for the CD2231 84
interrupt acknowledge 158
interrupt service requests 39
interrupts
170
acknowledge cycle 38
contexts and channels 37
groups and types 38
IACK cycles 39
keep and pass logic 40
multi–CD2430 systems 40
registers 37
systems with interrupt controllers 40
transmit and interrupt service requests 39
K
keep and pass logic 40
L
Local Loopback mode 112
logic, keep and pass 40
M
mapped characters
00–1F 70
20 and above 70
7D and 7E 70
FCS field, in the 70
Mark mode 67, 68
memory map 20
MNP4 mode 95
MNP4/SLIP mode 93
modes
Address Recognition mode 68
Addressing mode 90
Append mode 46, 55
Async-HDLC/PPP mode 94, 115, 119
Async-HDLC/PPP/MNP4 mode 128
Asynchronous DMA mode 56
Asynchronous mode 19, 97, 118, 128
Asynchronous/Async-HDLC/PPP
92
Autobaud mode 130
Chain mode 46
Clock 19
DPLL mode 110
FCS mode 96
mode
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