CD2231 Intel Corporation, CD2231 Datasheet - Page 34
Manufacturer Part Number
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
The CD2231 is a synchronous device with an asynchronous bus interface. A stable input clock is
required on the CLK pin — nominally 33 MHz. The CLK is divided by two (2) internally, and the
resulting signal is an output on the BUSCLK pin. The baud-rate generators and timers are also
related to CLK. The
setup and output signal transitions are related to the edges of the CLK and BUSCLK signals. It is
possible, however, to use the CD2231 in a purely asynchronous bus environment.
The CD2231 can act either as a bus master during DMA transfers, or as a bus slave device during
normal host read and write transfers. Both byte and word transfers are supported in each of the Bus
Slave and DMA Bus Master modes.
Host Read and Write Cycles
The host read and write cycles begin with the activation of the CS* (chip select) and DS* (data
strobe) signals. The DATADIR* (data direction) and DATEN* (data enable) signals control
external data buffers. The falling edge of the DTACK* (data transfer acknowledge) signal
indicates that the transfer is complete. At that time, DTACK* is released when DS* is deasserted.
CS* should also be deasserted. The AS* (address strobe) is not used during slave cycles; it is an
output during DMA transfers.
Note that the following open-drain and tristate outputs should have pull-up resistors attached:
AEN*, AS*, DATADIR*, DATEN*, and DTACK*.
“AC Electrical Characteristics”
show the signals involved in these
shows that many input signal