CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Figure 3. Host Write Cycle
CS*
DS*
R/W*
A/D[0–15]
A[0–7], SIZ[0–1]
DTACK*
DATEN*
DATDIR*
5.1.2
Byte and Word Transfers
Data can be moved to and from the CD2231 in either byte or word transfers. To accommodate
various families of host processors, the BYTESWAP input pin is set to indicate the system byte-
ordering scheme. The SIZ pins (SIZ[1, 0]) are used to indicate whether the transfer is 1 or 2 bytes
wide.
In systems where the even addresses represent the most-significant byte, the BYTESWAP input
pin should be tied low, and byte transfers occur on the A/D[15:8] pins for even addresses and on
the A/D[7:0] pins for odd addresses. In systems where the most-significant byte is on the odd
address, the situation is reversed, and BYTESWAP should be tied high. Byte transfers to even
addresses occur on the A/D[7:0] pins, and to odd addresses on the A/D[15:8] pins.
5.2
Interrupts
The CD2231 uses interrupt requests to alert the host that certain events have occurred. Interrupt
operations on the CD2231 are tightly coupled with several registers described later. The concept of
context affects the accessibility of these and other registers.
36
DIN
Datasheet