CD2231 Intel Corporation, CD2231 Datasheet - Page 4

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
6.0
7.0
4
5.5
5.6
Protocol Processing
6.1
6.2
6.3
6.4
6.5
6.6
Programming Examples
7.1
7.2
7.3
7.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
5.4.9
Bit Rate Generation and Data Encoding ............................................................. 57
5.5.1
Hardware Configurations .................................................................................... 64
5.6.1
5.6.2
5.6.3
HDLC Processing................................................................................................ 67
6.1.1
6.1.2
6.1.3
PPP (Point-to-Point Protocol) Mode.................................................................... 69
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
SLIP Processing.................................................................................................. 72
6.3.1
6.3.2
MNP‚4/ARAP Protocol Processing...................................................................... 73
6.4.1
6.4.2
Async Processing................................................................................................ 75
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
Non-8-Bit Data Transfers .................................................................................... 80
Global Initialization .............................................................................................. 85
Async Interrupt Setup Example........................................................................... 85
HDLC DMA Channel Setup Example.................................................................. 86
Receive DMA Interrupt Service Routine ............................................................. 86
Bus Acquisition Cycle............................................................................. 43
DMA Data Transfer ................................................................................ 43
Bus Error Handling................................................................................. 44
A and B Buffers and Chaining ................................................................ 45
Transmit DMA Transfer .......................................................................... 46
Synchronous Transmitter Examples ...................................................... 47
Receive DMA Transfer ........................................................................... 49
Transmit DMA Transfer .......................................................................... 52
Receive Buffer Interrupts ....................................................................... 55
BRG and DPLL Operation...................................................................... 57
Interface to a 32-Bit Data Bus ................................................................ 65
DMA Connections for the CD2231 ......................................................... 65
CD2231 as a DTE and DCE Interface.................................................... 65
Frame Check Sequence ........................................................................ 67
HDLC Transmit Mode............................................................................. 67
HDLC Receive Mode ............................................................................. 68
Character Format ................................................................................... 69
Frame Format ........................................................................................ 69
Frame Check Sequence ........................................................................ 69
Transparency ......................................................................................... 70
Definition of a Valid Frame..................................................................... 71
Transmitter ............................................................................................. 71
Receiver ................................................................................................. 72
Framing .................................................................................................. 73
Debugging Aids ...................................................................................... 73
Framing .................................................................................................. 74
MNP‚4/ARAP FCS (Frame Check Sequence) Calculation..................... 74
Transmitter In-Band Flow Control .......................................................... 75
Out-of-Band Flow Control ...................................................................... 77
Line Break Detection and Generation .................................................... 78
Special Character Transmission ............................................................ 78
Special Character Recognition and Special Character Range............... 79
Special Character Range ....................................................................... 79
UNIX‚ Support Features ......................................................................... 80
............................................................................................... 67
........................................................................................ 84
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