CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Page 31
32
Page 32
33
Page 33
34
Page 34
35
Page 35
36
Page 36
37
Page 37
38
Page 38
39
Page 39
40
Page 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Page 40/178

Download datasheet (3Mb)Embed
PrevNext
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Highest priority:
Lowest priority:
5.2.4.2
Systems with Interrupt Controllers
Some systems use an interrupt controller that supplies its own vector during the interrupt
acknowledge cycle. To function properly, the CD2231 needs an IACK cycle in response to its
interrupt request. These systems can decode three distinct locations from the CD2231 to produce
an IACKIN* instead of CS*. The PILRs should be programmed with the addresses of these three
locations.
Alternatively, a single location can be decoded and the three PILRs given identical values as
described earlier. In either case, the host should read one of these locations before the first access to
the device in an interrupt service routine. The CD2231 enters its interrupt acknowledge context for
the proper type and channel, and the data returned is the device interrupt vector from the LIVR.
5.2.5
Multi CD2231 Systems
Multiple CD2231s can be chained together for systems requiring more than two channels. Each
group of interrupt request lines — IREQn* — can be connected in a parallel wired-OR fashion.
The system Interrupt Acknowledge signal is connected to the IACKIN* pin of the first device, its
IACKOUT* is then connected to the IACKIN* of the next device, and so on, forming a chain of
CD2231s.
5.2.5.1
Keep-and-Pass Logic
The acceptance of an interrupt acknowledge cycle by the CD2231 depends on whether the part is
requesting service and whether the least-significant seven address bits match the contents of the
appropriate PILR. The following rules apply to the keep-and-pass logic:
1. If the CD2231 does not have an interrupt asserted, the interrupt acknowledge is passed out on
IACKOUT*.
2. If the CD2231 is asserting one or more of its interrupts, but the interrupt priority levels driven
on the address bus by the host do not match the contents of the appropriate PILR, this interrupt
acknowledge is also passed out on the IACKOUT*.
3. If the CD2231 is asserting an interrupt and the interrupt priority level on the address bus
matches the PILR for that interrupt type, the interrupt acknowledge is accepted by the
CD2231, and the vector from the LIVR is driven onto the data bus.
5.2.5.2
Fair Share Scheme
When multiple CD2231s are chained, the Fair Share logic in these devices guarantees that the
interrupts from all CD2231s in the system are presented to the host with equal urgency. There is no
positional hierarchy in the interrupt scheme. For example, the CD2231 farthest from the host has
an equal chance of getting its interrupts through as the CD2231 nearest to the top of the interrupt
chain. The Fair Share scheme is transparent to the user, and no enabling or disabling is required.
40
Receive Interrupt register
Transmit Interrupt register
Modem Interrupt register
Datasheet