CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
When an interrupt request line is asserted, the Fair bit for that type of interrupt on the asserting
device is cleared. The Fair bit remains cleared until the interrupt line returns to a high state. The
CD2231 does not assert a new interrupt of that type while the corresponding Fair bit is cleared.
Therefore, when multiple CD2231s assert interrupts together, each one is serviced in turn, before
they can reassert the same interrupt type.
The IREQn* lines are open-drain outputs that can be tied together in groups of the same type,
creating a Fair Share scheme for each group of interrupts. Alternatively, all three groups can be tied
to a common request using the CD2231 internal-priority scheme (see
5.3
FIFO and Timer Operations
Each channel in the CD2231 has a 16-byte receive FIFO and a 16-byte transmit FIFO. The FIFOs
are accessible through RDR (Receive Data register) and TDR (Transmit Data register) registers.
These Virtual registers are shared among the two channels; therefore, they cannot be accessed
outside an interrupt context.
The threshold level of each channel is common for both FIFOs and is set by COR4 (Channel
Option Register 4), with a maximum threshold value of 12. The FIFO threshold is meaningful in
both DMA and non-DMA modes. In DMA mode, the FIFO threshold determines when transfer
bursts should occur. In non-DMA mode, the threshold level determines when transfer interrupts are
asserted.
5.3.1
Receive FIFO Operation
In the Asynchronous mode, a Good Data interrupt is initiated when the number of characters in the
FIFO is greater than the FIFO threshold. Note that receive timeout and receive data exception
conditions also cause an interrupt to the host.
In the Synchronous mode, an interrupt request for data transfer is initiated when the number of
characters is greater than the FIFO threshold or an end of frame is reached.
5.3.2
Transmit FIFO Operation
The TxDat and TxEmpty bits in the IER control the generation of transmit FIFO interrupts. The
CD2231 initiates an interrupt request for more data when the number of empty bytes in the FIFO is
greater than the threshold set. During synchronous operation when the last byte of the frame is
transferred to the FIFO, the CD2231 stops asserting transmit interrupts until the frame is sent.
5.3.3
Timers
The global TPR (Timer Period register) provides a timer prescale ‘tick’ as a clock source for the
timers. The TPR counter is clocked by the system clock (CLK) divided by 2048. To maintain timer
accuracy, the TPR should not be programmed with a value less than 16 (10 hex) — a ‘tick’ of about
1 millisecond when CLK is 33 MHz.
Each channel has two timers: one 16-bit general timer 1 (GT1), and one 8-bit general timer 2
(GT2). Their operation and programming are different in synchronous and asynchronous protocols.
Datasheet
Section
5.2.4.1).
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