CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
If there is a non-zero value in the BERCNT (Bus Error Retry Count register), the register is
decremented and the failed transfer is retried automatically. If the BERCNT is zero, a bus error
interrupt is generated and DMA transfers are suspended on the failing buffer until the interrupt is
serviced.
5.4.4
A and B Buffers and Chaining
The buffer management of the CD2231 uses a dual-buffer scheme. There is an A and B buffer pair
for each transmitter and each receiver. Each buffer is controlled by an Ownership Status bit, called
2231own. When 2231own is set to ‘1’, the CD2231 ‘owns’ the buffer. When 2231own is set to ‘0’,
the host ‘owns’ the buffer. A simple rule prevents confusion in the buffer management — neither
the CD2231 nor the host seizes buffer ownership. Each always relinquishes ownership to the other.
The host relinquishes ownership of a receive buffer to the CD2231 when the receive buffer is
ready. The CD2231 is then free to write received data into the buffer. The CD2231 returns
ownership of the receive buffer after the receive data is in the buffer. The host gives ownership of a
transmit buffer to the CD2231 when the transmit buffer is ready to transmit. The CD2231 then
transmits the contents of the buffer. When this is complete, the CD2231 returns ownership back to
the host.
The CD2231 keeps track of which buffer (A or B) is to be used next in the status bits — Ntbuf for
transmit and Nrbuf for receive. The relationship between the 2231own bit and the ‘next’ bits is
shown later. The receive buffers are handled in the same way using the Nrbuf (next receive buffer).
Chaining is used to break up relatively long frames into shorter blocks in memory, and is useful
where there are frequent smaller frames and occasional long frames. Chaining allows more
efficient use of the user RAM.
The EOF Status bit controls chaining in Synchronous modes. Chaining applies to both transmit and
receive. For transmit, the host determines the EOF bit; for receive, the CD2231 determines the
EOF bit.
In Transmit DMA, when the first buffer is supplied to the CD2231, it is treated as the start of frame
— the CRC is reset and leading pad/flag/syn characters are transmitted, followed by the data. If the
EOF bit is set, the CRC and closing flag/syn is appended, and the next buffer is again treated as the
start of frame. If the EOF bit is not set, the CD2231 treats the buffer as the first part of a larger
frame and chains into the next buffer (does not reset CRC); this process continues until a buffer is
supplied with the EOF bit set.
Table 3. A and B Buffers Chaining (Sheet 1 of 2)
2231own
Ntbuf
Buffer A
0
0
1
1
1
0
Datasheet
2231own
Buffer B
0
0
Send nothing
1
0
Host sets up Buffer A
1
0
CD2231 accepts Buffer A and marks B as next
0
0
CD2231 completes A Tx, and passes it to host
0
1
Host sets up Buffer B
0
1
CD2231 accepts B and marks A as next
Transmit Action
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