CD2231 Intel Corporation, CD2231 Datasheet - Page 47

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

5.4.6
Datasheet
Figure 7. Transmitter A and B Buffers
NOTE: Number of bits in each register is shown in parentheses ( ). Buffer
count. In this case, ATBCNT should be written as a 16-bit word to avoid confusion between two
byte operations. The ATBADR[0–3] should not be reprogrammed during the Append mode. If the
memory space has to be moved, the Append mode must be disabled first. When the final data is
added to the append buffer and ATBCNT has been updated, the host should set the AppdCmp bit
(STCR[5]). When the CD2231 has completed the final transmission, it clears the 2231own bit in
the ATBSTS register, and generates an end-of-buffer interrupt.
Synchronous Transmitter Examples
In
(DMABSTS, ATBADR, TCBADR, ATBCNT, ATBSTS, BTBADR, BTBCNT, and BTBSTS) are
inside the CD2231.
Example 1
Transmit a frame out of channel 1, with no chaining.
1. The host checks the Ntbuf bit in the DMABSTS register for channel 1 to determine which
2. The host sets up the buffer data, the starting address — ATBADR, and the buffer byte count
3. The host sets up the ATBSTS (‘A’ Buffer Status) register. The EOF bit is set to indicate that
4. The CD2231 starts frame transmission out of channel 1. When transmission is started, the
Figure
A and Buffer B do not need to be the same length.
buffer is next. In this example, Ntbuf is set to ‘0’ indicating that Buffer A is used next.
— ATBCNT.
there is no chaining. The 2231own bit is set to give ownership to the CD2231. By setting
2231own, the host commands the CD2231 to start transmission. Thus, everything must be
ready (starting address, buffer data, and byte count) prior to setting 2231own.
CD2231 sets Tbusy bit in DMABSTS. As transmission progresses, the current buffer pointer
(TCBADR) is updated by the CD2231. Also, at the start of transmission, the Ntbuf bit (Next
Buffer) is set to ‘1’ to notify the host that Buffer B is next.
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
7, buffers A and B are contained in RAM external to the CD2231. All others
CD2231 Transmit
DMA Registers
(Currently using Buffer A)
BTBADR (32)
ATBADR (32)
TABADR (32)
BTBCNT (16)
ATBCNT (16)
ATBSTS (8)
BTBSTS (8)
(Status register)
(Status register)
Starting Address
Starting Address
Buffer Byte Count
Current Count
Buffer Byte Count
Physical
Memory
Transmit
Transmit
Buffer
Buffer
A
B
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