CD2231 Intel Corporation, CD2231 Datasheet - Page 49

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

5.4.7
Datasheet
Receive DMA Transfer
In all protocol modes, two host memory buffers can be made available to each receive channel, by
the ARBADR/BRBADR and ARBCNT/BRBCNT (Receive Buffer Address and Receive Buffer
Count registers) registers. To make a buffer available, the user must supply the buffer address in
the Receive Buffer Address registers; the number of free bytes in the buffer must be written in the
Receive Buffer Count registers, and the buffer status must be updated in the ARBSTS/BRBSTS
(Receive Buffer Status register) registers. The CD2231 is then free to use the buffer for receive
data, and updates the Buffer Status register as appropriate. When the buffer is no longer in use, the
CD2231 writes the number of bytes stored in the buffer in RBCNT and updates status in RBSTS.
This frees the host to take control of this buffer and supply a new buffer in its place. The CD2231
automatically switches to the other buffer whenever one buffer becomes full, or the end of a frame
has been reached. If the other buffer has not been allocated, the host still has the time required to
fill the CD2231 16-byte FIFO, to respond, and to avoid loss of data.
Special actions are taken depending on the channel protocol. In HDLC, PPP, SLIP and MNP 4, the
end-of-frame/data block boundaries are recognized by the CD2231. When a data-block boundary is
detected, the current buffer is automatically terminated. If the other buffer is allocated and owned
by the CD2231, it becomes the current buffer. End-of-frame and block interrupts are also generated
to the host.
In Asynchronous mode, a host interrupt is generated when there are receive exceptions (framing
error, special character, etc.), but the buffer is not terminated. The data and exception status are
made available to the host, just as when the Asynchronous mode is purely interrupt-driven. New
data is buffered internally in the FIFO until the host services the exception interrupt. The host has
the following three options when terminating an exception interrupt:
These selections are communicated to the CD2231 by the value written by the host to the Receive
End of Interrupt register, when the Receive Interrupt service is completed. Leaving an ‘n’-byte gap
enables the host to insert status of its own in the current buffer, while continuing to receive data in
the same buffer. This eliminates the overhead of allocating a new buffer. The host must have noted
the starting location of the gap while in the exception interrupt. This is done by reading the Receive
Current Buffer Address register. The address in this register is guaranteed to be stable during the
Receive interrupt, and point to the next free character location in the current DMA buffer. If the
12. The CD2231 optionally interrupts the host with bit EOF clear and bit EOB set in the TISR to
13. By this time, the host has set up a new buffer for Buffer B. The EOF bit in the BTBSTS is set
14. The CD2231 transmits Buffer B in the same manner as explained earlier. As before, the
15. When the CD2231 completes transmission, any necessary CRCs and ending frame delimiters
16. The CD2231 optionally interrupts the host with EOF and EOB bits set in the TISR to indicate
1. The exception character can be discarded.
2. The buffer can be terminated (if there is no additional interrupt to be generated). The transfer
3. A user-defined gap can be left in the buffer.
indicate that the transmission has completed, and that there was chaining.
to indicate that this is the last link in the chain.
CD2231 transmits the number of bytes indicated in the BTBCNT, which is 40 bytes for the
third segment.
are transmitted.
that the transmission has completed, and that this was the last link in the chain.
count is not provided in ARBCNT/BRBCNT, but can be calculated by RCBADR.
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
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