CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Page 51
52
Page 52
53
Page 53
54
Page 54
55
Page 55
56
Page 56
57
Page 57
58
Page 58
59
Page 59
60
Page 60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Page 57/178

Download datasheet (3Mb)Embed
PrevNext
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
To retry the buffer from the failure point, the CPU should set the 2231own bit in the ARBSTS/
BRBSTS register. The CPU should not set the TermBuff bit when writing to REOIR at the end of
the interrupt, this causes the last transfer to be retried. Should a bus error occur again, the above
procedure is repeated. The CPU should check to ensure that a bad location is not continually
retried.
5.5
Bit Rate Generation and Data Encoding
5.5.1
BRG and DPLL Operation
Data clocks are generated in the CD2231 by feeding one of a number of clock sources into a
programmable divider. The clock source and divisor are separately programmable for each channel
and direction by the user. Clock options are programmed in the Transmit Clock Option and
Receive Clock Option registers. The divisors are programmed in the Transmit Bit Rate Period and
Receive Bit Rate Period registers. The possible clock sources are as following:
Transmit
1. Clk 0 – CLK input 8
2. Clk 1 – CLK input 32
3. Clk 2 – CLK input 128
4. Clk 3 – CLK input 512
5. Clk 4 – CLK input 2048
6. TXCIN pin
7. Receive bit clock
Receive
1. Clk 0 – CLK input 8
2. Clk 1 – CLK input 32
3. Clk 2 – CLK input 128
4. Clk 3 – CLK input 512
5. Clk 4 – CLK input 2048
6. RXCIN pin
The CLK input is nominally 33 MHz.
The divisor can be programmed for values from 1–255. To maximize the accuracy of edge
detection in Asynchronous and DPLL (digital phase locked loop) modes, select the highest
frequency clock and largest divisor combination.
An external clock input can be used and used as a multiple of the desired bit rate. If so, the
appropriate divisor value must be loaded into the Bit Rate Period register. If the external clock is at
the desired bit rate (1 clock), a value of 01h must be loaded into the associated Bit Rate Period
register.
Datasheet
57