CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


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Page 62/178

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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Table 8.
Bit Rate Constants, CLK = 35 MHz (Sheet 2 of 2)
Bit Rate
4800
7200
9600
19200
38400
56000
64000
76800
115200
12800
134400
NOTE: All divisors are in hexadecimal.
Transmit and receive data can be encoded and decoded in NRZ, NRZI, or Manchester formats. For
NRZI, at the start of transmission, a learning datastream of contiguous zeros achieves bit
synchronization; for Manchester, an alternating pattern of ones and zeros is required.
NRZ, NRZI, and Manchester are data encoding schemes used in various synchronous protocols. In
NRZ, the signal condition represents the data type, high for a logic ‘1’ and low for a logic ‘0’. In
NRZ and NRZI encoding, the transitions of the datastream occur at the beginning of the bit cell. In
NRZI encoding, the signal condition switches to the opposite state to send a binary ‘0’. In
Manchester encoding, the transitions are always in the middle of the bit cell. A high-to-low
transition is made to send a logic ‘1’, and a low-to-high transition to send a logic ‘0’. The timing
diagrams
(Figure 11
Example 3
This example illustrates programming the DPLL at 128 kbits/second in NRZI mode, using the
internal clock at a system clock frequency of 33 MHz.
Divisor loaded into RCOR = 38 or 26h
Value loaded into RCOR = 28h, to enable the DPLL, NRZI framing and select Clk 0
Example 4
This example illustrates programming the DPLL in the 1 External Clock mode, with Manchester
encoding.
Divisor loaded into RBPR = 01h, to enable 1 external clock
Value loaded into RCOR = 36h, to enable the DPLL, select Manchester framing, and external
clock
When using an n-times external clock, the highest possible clock frequency and largest divisor
combination is recommended. The frequency of an external clock should be less than the system
CLK input divided by 16, (that is, for 33-MHz operation, the data clock should be less than 2.0
MHz). Note that R(T)BPR is an 8-bit register, therefore the largest divisor value is 255.
62
Divisor
Clock
e3
Clk 1
97
Clk 1
71
Clk 1
e3
Clk 0
71
Clk 0
4d
Clk 0
43
Clk 0
38
Clk 0
25
Clk 0
21
Clk 0
20
Clk 0
to
Figure
13) illustrate the encoding method. The data bits are ‘0110010’.
Error
0.06%
0.06%
0.06%
0.06%
0.06%
0.16%
0.53%
0.06%
0.06%
0.53%
1.38%
Datasheet