CD2231 Intel Corporation, CD2231 Datasheet - Page 72

• Manufacturer Part Number: CD2231
• Description: CD2231 Intelligent Two-channel Lan And Wan Communications Controller
• Manufacturer: Intel Corporation

CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
6.2.6.3
6.2.6.4
6.2.7
6.2.7.1
6.2.7.2
6.3
72
(COR3)
Option
RxChk
RTPR
Note: SLIP, MNP 4, and Automatic In-Band Flow Control modes are only available on Revision B and
Transmission of Abort
When commanded through a bit in the STCR (Special Transmit Command register), the device
ends the transmission of the current frame with an abort sequence of 7D–7E. After executing the
abort, the device clears the STCR. The rules for shared flag transmission in
followed for the trailing flag (7E) of the abort sequence (7D–7E).
If the device is not sending a frame when the Command bit is set, the device clears the STCR and
does not send an abort sequence.
Transmit Framing Error
For test purposes, one character with a framing error can be transmitted inside a frame. A
Command bit in the STCR notifies the device to transmit one character with Stop bit forced to ‘0’.
If the channel is transmitting a frame, one framing error character is inserted. After transmission,
the channel continues with the frame transmission. After executing the command, the device clears
the STCR.
If the device is not sending a frame when the Command bit is set, the device clears the STCR and
does not send a framing error character.
Receiver
Fixed Receiver Operations
The receiver accepts a frame or a character when the received data is brought through the device
and presented to the host.
In Async-HDLC mode, the receiver accepts only characters of the format shown in
The receiver accepts only frames that have an opening flag; there can be more than one opening
flag.
Receiver Options
The device receiver can be control-bit selected for the following options:
SLIP Processing
later devices.
If RxChk is set, the receiver tests the FCS at the end of each frame and reports the result.
If RxChk is clear, the receiver makes no FCS computation.
The RTPR timer is disabled when all bits are zero. RTPR is enabled with a non-zero value.
See
Section
6.5.
Description
Section 6.2.6.2
Section
Datasheet
are
6.2.1.