CD2231 Intel Corporation, CD2231 Datasheet - Page 78

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
6.5.3
6.5.4
78
Table 14. Datastream Transmission Breaks
used, then DTR goes inactive when the receive FIFO reached the programmed threshold, thus
causing the modem to drop the connection (carrier) to the remote; this would not be the correct
function based on the state of the receive FIFO.
Line Break Detection and Generation
A line break on the receiver occurs when the input at the RXD (receive data) pin is all zeros (low)
for at least one full character time. This is indicated when the Break bit (RISRL[0]) is set to ‘1’.
Line-break generation out of the transmitter is possible when the ETC (Embedded Transmit
Command) bit (COR2[5]) is set to ‘1’. A line break is generated when the output at the TXD
(transmit data) pin is all zeroes (low) for at least one full character time.
Line breaks can be transmitted by embedding certain sequences in the data stream as defined in
Table
sequences to transmit a break are listed in
The ETC mechanism works in ASYNC mode only, though breaks can be detected in ASYNC,
PPP, SLIP, and MNP4 modes.
NOTE: In addition to insert delay, a ‘break’ can also be increased beyond one full character by transmitting
Special Character Transmission
Selected special characters can be sent preemptively by setting the SndSpc (Send Special Character
Command) bit in the STCR. The CD2231 channel acknowledges the command by clearing the
STCR. Along with the SndSpc bit, the host needs to set-up the three Special Character Select
(SSPC0, SSPC1, SSPC2) bits, also in the STCR, to select which character is to be sent.
When the host commands a special character transmission, the channel completes transmitting any
characters in the Transmit Shift register and Transmit Holding register, and then transmit the
special character sequence. Any other characters awaiting transmission in the FIFO or through
DMA are transmitted after the special character.
If the transmitter is off due to in-band flow control, the special characters override and are sent.
Special characters override out-of-band flow control. Also if the transmitter is disabled, the special
character send command overrides and the character are sent.
00h–81h
00h–82h-xxh
00h–83h
00h–00h
14. These sequences are valid for transmitting breaks only if ETC is set to ‘1’. The embedded
more than one ‘send BREAK’ sequence at a time.
Send BREAK – Send a line break for at least one character time.
Insert delay – To increase the break generation beyond one character time, the insert
delay sequence can be used. The inserted delay is xx, where xx is a binary number. The
delay is xx times the ‘tick’ set by the TPR (Timer Period register). The minimum period of
TPR should be 1 millisecond. If the insert delay sequence is not preceded by a send
BREAK sequence, there is an inserted delay of all ‘1’s (high) on the output for duration xx.
Stop BREAK – This must follow the send BREAK sequence, or the insert delay sequence.
Send NUL – If the user needs to send a NUL character and ETC = 1, the user can embed
00h–00h to send one NUL character. If there are less than 8 bits per character, the user
can also send a NUL character by ‘sending’ an 80h.
Table
14.
Datasheet

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