CD2231 Intel Corporation, CD2231 Datasheet - Page 85

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CD2231

Manufacturer Part Number
CD2231
Description
CD2231 Intelligent Two-channel Lan And Wan Communications Controller
Manufacturer
Intel Corporation
Datasheet
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7.1
7.2
Datasheet
Global Initialization
The following code segment is an example of global initialization. The host waits for a hardware
reset, determined by a non-zero value in the GFRCR (Global Firmware Revision Code register). A
‘RESET ALL’ command is sent to the CD2231 through the CCR (Channel Command register).
The internal processor puts a non-zero value into the GFRCR when initialization is complete. It is
recommended to manually clear the GFRCR before issuing the Reset All command, as it takes a
small amount of time for the internal processor to detect the command and clear the register. If the
host is sufficiently fast, it might read the GFRCR before the command execution commences and
incorrectly assumes the command is completed.
The Priority Interrupt Level registers should be loaded with the value of the seven address lines
(A[6:0]) during interrupt acknowledge cycles. The TPR (Timer Prescale register) loads the
dividing counter that inputs each of the other timers in the CD2231. The DMA Mode register and
the Bus Error Count register are used in DMA modes only. After the global portion is done, the
Per-Channel registers need to be initialized. Transfers and interrupts should be enabled after all
other initialization is complete.
// Global Initialization
// per-channel initialization
Async Interrupt Setup Example
This section contains a code example for an asynchronous channel running at 19,200 bps, with 8
bits/character, 1 Stop bit, and no parity. The sample program enables In-Band Flow Control and
Implied Xon mode. This code assumes that the proper channel is set by the CAR (Channel Access
register).
Intelligent Two-Channel LAN and WAN Communications Controller — CD2231
while( !inportb( GFRCR ) )// wait for hardware reset
outportb( GFRCR, 0x00 );// manually clear GFRCR
outportb( CCR, RESET_ALL );// Reset command
while( !inportb( GFRCR ) ) // wait for reset command
outportb( PILR1, 0x02 );// Priority Interrupt
outportb( PILR2, 0x04 );// Level Registers
outportb( PILR3, 0x06 );
outportb( TPR, 0x40 ); // Set timer prescale
outportb( BERCNT, 0 ); // Bus error count
outportb( DMR, 0 );
for( i=0; i<2; i++ ) {
}
outportb( LIVR, 0x40 );
outportb( RCOR, 0 );
outportb( RBPR, 0x81 );// Baud Rate divisor
outportb( TCOR, 0 );
outportb( TBPR, 0x81 );// Baud Rate divisor
outportb( CAR, i );// set channel number
init_chan( cor, bpr );// initialize channel
outportb( CCR, INIT_CH | EN_RX | EN_TX );
while( inportb(CCR) )
outportb( IER, TX_DATA|RX_DATA );// enable interrupts
; // wait
; // wait
; // wait
// DMA mode — 16-bit
// Receive clock option
// Transmit clock option
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