CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Page 88/178

Download datasheet (3Mb)Embed
PrevNext
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.0
Detailed Register Descriptions
8.1
Global Registers
8.1.1
Global Firmware Revision Code Register (GFRCR)
Register Name: GFRCR
Register Description: Global Firmware Revision Code
Default Value: x’0D
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
This register serves two functions in providing the host with information about the CD2231. When
a hardware RESET* signal, or a software RESET ALL command is issued through either of the
two Channel Command registers, it initializes the CD2231 and zeroes this register at the start of the
initialization. At the end of the initialization, the CD2231 writes its firmware revision code to the
GFRCR. All valid CD2231 revision codes are non-zero and the revision code is incremented by
one with each new release (for example, GFRCR for Revision D = 34 hex).
Host software must confirm that the GFRCR contents are non-zero before proceeding to configure
the CD2231 for normal operation.
8.1.2
Channel Access Register (CAR)
Register Name: CAR
Register Description: Channel Access
Default Value: x’03
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
0
0
0
This register contains the channel number for the channel-oriented host read or write operations
when the host is not in an interrupt service routine. The CD2231 supplies the interrupting channel
number during all interrupt service operations. The Channel Access register contents are not used
during an interrupt service. Note that this means that an interrupt service routine is restricted to
accessing only the register set of the Interrupting Channel and Global registers.
Bits 7:1
Reserved – must be ‘0’.
Bit 0
Channel number
88
Bit 4
Bit 3
Bit 2
Firmware revision code
Bit 4
Bit 3
Bit 2
0
0
0
Intel Hex Address: x’82
Motorola Hex Address: x’81
Bit 1
Bit 0
Intel Hex Address: x’EC
Motorola Hex Address: x’EE
Bit 1
Bit 0
0
C0
Datasheet