CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 
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Page 90/178

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CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
8.2.2
Channel Option Register 1 (COR1)
8.2.2.1
COR1 — HDLC Mode
Register Name: COR1
Register Description: Channel Option Register 1
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
AFLO
ClrDet
AdMd1
If any options specified in this register are changed, an initialize command must be given to
CD2231 through the Channel Command register.
Bit 7
Address field length option
0 = Address field is 1 octet in length
1 = Address field is 2 octets in length
Bit 6
Clear detect for X.21 data transfer phase
0 = Clear detect disabled
1 = Clear detect enabled
A clear is defined as two consecutive all-zero receive characters with the CTS* pin
high.
Bits 5:4
Addressing modes
00 = no address recognition
01 = 4 * 1 byte
10 = 2 * 2 byte
If this bit is set, RFAR1, RFAR2, RFAR3, and RFAR4 should contain the address
to be matched. If AFLO is set to ‘1’, an address match is made against the RFAR1
and RFAR2 pair or the RFAR3 and RFAR4 pair.
Bits 3:0
Inter-frame flag option
Defines the minimum number of flags transmitted before a frame is started.
Flags 3
The minimum number of opening flags always precede a frame when idle in Mark
mode is set, or is always separated by two consecutively transmitted frames. No
restriction is placed on the number of flags between received frames.
90
Bit 4
Bit 3
AdMd0
Flag3
Flags 2
Flags 1
Flags 0
0
0
0
0
0
0
0
1
through
1
1
1
1
Intel Hex Address: x’13
Motorola Hex Address: x’10
Bit 2
Bit 1
Bit 0
Flag2
Flag1
Flag0
minimum of 1 opening flag, with shared
closing/opening flags permitted
minimum number of opening flags sent
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