CD2231

Manufacturer Part NumberCD2231
DescriptionCD2231 Intelligent Two-channel Lan And Wan Communications Controller
ManufacturerIntel Corporation
CD2231 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
Page 91
92
Page 92
93
Page 93
94
Page 94
95
Page 95
96
Page 96
97
Page 97
98
Page 98
99
Page 99
100
Page 100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
Page 98/178

Download datasheet (3Mb)Embed
PrevNext
CD2231 — Intelligent Two-Channel LAN and WAN Communications Controller
Bit 5
FCT – Flow Control Transparency mode
0 = Flow control characters received are passed to the host by receive exception
interrupts.
1 = Flow control characters received are not passed to the host.
This bit has no effect unless both TxIBE (COR2[6]) and SCDE (COR3[4]) are set.
Bit 4
SCDE – Special character detection
0 = Special character detect for SCHR1 and 2 is disabled.
1 = Special character detect for SCHR1 and 2 is enabled.
This bit must be set along with TxIBE (COR2[6]) before FCT (COR3[5]) becomes
effective.
Bit 3
Splstp – Special character I-strip
When set, this bit causes the receive character to be I-stripped (COR3[7] set to ‘0’)
for the special character matching functions only. The character passed to the host is
unaffected. This function allows special character processing of data without know-
ing if the data is 8 bits with no parity or 7 bit with parity.
Bits 2:0
Stop2, Stop1, Stop0 – Stop bit length
Specifies the length of the Stop bit.
8.2.5
Channel Option Register 4 (COR4)
Register Name: COR4
Register Description: Channel Option Register 4 (Modem Change Options
and FIFO Transfer Threshold)
Default Value: x’00
Access: Byte Read/Write
Bit 7
Bit 6
Bit 5
DSRzd
CDzd
CTSzd
(Modem Change Options and FIFO Transfer Threshold)
Bit 7
DSRzd = 1
Detect one-to-zero transition on the DSR* input (zero-to-one transition of DSR
(MSVR) bit)
Bit 6
CDzd = 1
Detect one-to-zero transition on the CD* input (zero-to-one transition of CD
(MSVR) bit)
Bit 5
CTSzd = 1
Detect one-to-zero transition on the CTS* input (zero-to-one transition of CTS
(MSVR) bit)
Bit 4
Reserved – must be ‘0’.
98
Stop2
Stop1
Stop0
0
1
0
0
1
1
1
0
0
000–001 and 110–111 are reserved.
Bit 4
Bit 3
0
Stop Bit Length
1 stop bit
1.5 stop bits
2 stop bits
Intel Hex Address: x’16
Motorola Hex Address: x’15
Bit 2
Bit 1
Bit 0
FIFO threshold
Datasheet