S1D13742 Epson, S1D13742 Datasheet

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S1D13742

Manufacturer Part Number
S1D13742
Description
Mobile Graphics Engine
Manufacturer
Epson
Datasheet
S1D13742 Mobile Graphics Engine
Hardware Functional Specification
Document Number: X63A-A-001-06
Status: Revision 6.01 - EPSON CONFIDENTIAL
Issue Date: 2007/09/18
www.DataSheet.co.kr
© SEIKO EPSON CORPORATION 2004 - 2007. All Rights Reserved.
You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products.
You may not modify the document. The Programs/Technologies described in this document may contain material protected under U.S. and/or
International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
Datasheet pdf - http://www.DataSheet4U.net/

Related parts for S1D13742

S1D13742 Summary of contents

Page 1

... S1D13742 Mobile Graphics Engine Hardware Functional Specification Document Number: X63A-A-001-06 Status: Revision 6.01 - EPSON CONFIDENTIAL Issue Date: 2007/09/18 © SEIKO EPSON CORPORATION 2004 - 2007. All Rights Reserved. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. ...

Page 2

... Page 2 S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2007/09/18 Datasheet pdf - http://www.DataSheet4U.net/ ...

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... Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.2 PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 RESET# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.3 Host interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Hardware Functional Specification Issue Date: 2007/09/18 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 3 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 4

... Mode 1 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . . . . . . . . . . . . .79 12.3 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors . . . . . . . . . . . . . .80 12.4 24 bpp Mode 1 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors 12.5 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors 13 YUV Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 13.1 YUV 4:2:2 with Intel 80, 8-bit Interface . . . . . . . . . . . . . . . . . . . . .84 S1D13742 X63A-A-001- .41 www.DataSheet.co. .75 Revision 6.01 - EPSON CONFIDENTIAL ...

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... Opening Multiple Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 17.1.5 Individual Memory Location Reads . . . . . . . . . . . . . . . . . . . . . . . . . . 102 18 Double Buffer Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 18.1 Double Buffer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 103 19 Interfacing the S1D13742 and a TFT Panel . . . . . . . . . . . . . . . . . . . . . . 106 19.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 19.1.1 Electrical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 19.1.2 S1D13742 Register Settings for 352x416 TFT Panel . . . . . . . . . . . . . . . . . 107 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel . . . . . . . . . . . . . . . . . 109 19 ...

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... PLL Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 123 20.1 Guidelines for PLL Power Layout . . . . . . . . . . . . . . . . . . . . . . 123 21 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 22 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 23 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 23.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2007/09/18 Datasheet pdf - http://www ...

Page 7

... We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com. 1.2 Overview Description The S1D13742 is a color LCD graphics controller with an embedded 768K byte display buffer. The S1D13742 supports a 8/16-bit Intel 80 CPU architecture while providing high performance bandwidth into display memory allowing for fast screen updates. ...

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... LUT’s are placed on the display side and therefore do not affect the data stored in memory. 3. RGB (5:6:5) stored in memory: LUT is by-passed. Copy msb to lsb for red and blue during the display read from memory. S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development ...

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... General Purpose Input/Output pins are available (GPIO[7:0]). • INT pin associated with selectable GPIO inputs. • Package: Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr FCBGA 121-pin package QFP20 144-pin package Revision 6.01 - EPSON CONFIDENTIAL Page 9 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 10

... Page 10 3 Block Diagram MClk Intel 80 MClk MClk 8/16 IF YUV YUV to Converter RGB Registers RegWrClk Clocks Test Mux S1D13742 X63A-A-001-06 MClk MClk MClk Rotation LCD Disp Memory Pipe Controller (Pixel Halving) MClk Double Buffer Controller Figure 3-1: Block Diagram www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL ...

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... CNF1 H GPIO2 GPIO3 CNF2 J GPIO4 GPIO5 PWRSVE K NC GPIO6 GPIO7 VD6 Figure 4-1: S1D13742 FCBGA Pinout (Top View) Hardware Functional Specification Issue Date: 2007/09/18 CLKI MD3 MD4 MD5 MD13 MD14 MD15 IOVDD VSS VSS CS# PLLVDD VCP PLLVSS COREVDD VSS VSS ...

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... Figure 4-2: S1D13742 QFP20 Pinout (Top View) S1D13742 X63A-A-001- www ...

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... L System is COREVDD (see Section 6, “D.C. Characteristics”). 3 LVCMOS is Low Voltage CMOS (see Section 6, “D.C. Characteristics”). Hardware Functional Specification Issue Date: 2007/09/18 Table 4-1: Cell Description Description 3 Input Buffer www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 13 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

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... For the S1D13742B00, when the 8-bit bus interface is selected by CNF1, MD[15:8] are pulled low by internal resistors. • For the S1D13742B01, when the 8-bit bus interface is selected by CNF1, MD[15:8] should be connected to VSS. Note: The Host Data lines can be swapped (i.e. MD15 = MD0) using the CNF0 pin. For details, see Section 4.3, “ ...

Page 15

... CNF2 pin. For details, see Section 4.3, “Summary of Configuration Options” on page 18. This output pin is the Vertical Sync L pulse L This output is the Horizontal Sync pulse L This output pin is the Data Clock L This output pin is the Data Enable X63A-A-001-06 Page 15 S1D13742 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 16

... TESTEN K3,K2, 71,79,81, J2,J1, GPIO[7:0] IO 82,84,83, H2,H1,G 87, PWRSVE S1D13742 X63A-A-001-06 Table 4-4: Clock Input Pin Descriptions Power IO RESET# Cell Save Voltage State Status MHz input for PLL operation or MHz input if PLL is bypassed HIS IOVDD Input Input Input frequency range: 1MHz ~ 33MHz This output pin represents the CLKI pin if enabled by CLKOUTEN ...

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... This pin should be left unconnected for normal operation. This is the PLL VCP Test pin and is used for production test only. This pin should be left unconnected for normal operation. These pins are not connected. Description S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 18

... When CNF1=0, all Register access is 8-bit only. When CNF1 =1 (16-bit): All Register access is 8-bit ONLY (the most significant byte on the data bus is ignored) except the Memory Data Port. Access to the Mem- ory Data Port is 16-bit. S1D13742 X63A-A-001-06 Power-On/Reset State Host Data Lines are swapped: If CNF1 = 1, then D15 = D0, etc ...

Page 19

... Epson Research and Development Vancouver Design Center 5 Pin Mapping 5.1 Intel 80 Data Pins This function is controlled by CNF [1:0] Table 5-1: S1D13742B00 Intel 80 Data Pin Mapping 16-Bit Data Pin Name No Swap (CNF1=1, CNF0=1) MD15 • • • MD8 MD7 • • • MD0 Table 5-2: S1D13742B01 Intel 80 Data Pin Mapping ...

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... VD30 driven 0 driven 0 VD31 driven 0 driven 0 VD32 driven 0 driven 0 VD33 driven 0 driven 0 VD34 driven 0 driven 0 VD35 driven 0 driven 0 S1D13742 X63A-A-001-06 16bpp Double (36-bit) Single (18-bit) Normal Swap Normal Vertical Sync Horizontal Sync Pixel Clock Data Enable ...

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... VD0 VD35 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 21 18-Bit Data Swapped REG[14] b7=1 Driven Low • • • • • • Driven Low VD17 VD0 • • • • • • VD0 VD17 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

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... There are no special Power On/Off requirements with respect to sequencing the various VDD pins. There are also no special requirements for the IO signals, however Inputs should not be floating. If the input signals were to power valid cycle, the S1D13742 would decode the cycle. S1D13742 X63A-A-001-06 Table 6-1: Absolute Maximum Ratings VSS - 0 ...

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... IOVDD V — PIOVDD V — PIOVDD V — 0.40 V — 0.40 V — 0.40 V — — V — — V — 0.57 V — 0.57 V — 1.56 V — 1.27 V — — V 100 240 kΩ 100 240 kΩ 200 480 kΩ 200 480 kΩ — S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

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... COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V 2. Typical Operating Current Environment: 800 x 480 TFT panel with PCLK divide by 3. SYSCLK= 59MHz from PLL, PLL Source from 12MHz CLKI input. 16bpp memory storage. COREVDD and PLLVDD to 1.5V, HIOVDD, PIOVDD to 2.8V S1D13742 X63A-A-001-06 Condition Min CLKI stopped (grounded), Sleep Mode enabled, all power — ...

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... IOVDD V — PIOVDD V — PIOVDD V — 0.40 V — 0.40 V — 0.40 V — — V — — V — 0.80 V — 0.80 V — 2.70 V — 1.80 V — — 120 kΩ 50 120 kΩ 100 240 kΩ 100 240 kΩ — S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

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... Panel/GPIO Interface) L 7.1 Clock Timing 7.1.1 Input Clocks 90 CLKI CLKI S1D13742 X63A-A-001-06 and T for all inputs except Schmitt and CLKI must be < (10% ~ 90%) fall and T for all Schmitt must be < (10% ~ 90%) fall t1 t4 www.DataSheet.co.kr t OSC t ...

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... Parameter www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 27 Min Typ Max Units 1 — 66 MHz 0 — 68.90 MHz μs — 1/f — OSC μs 0.4t — 0.6t OSC OSC 0.4t — 0.6t μs OSC OSC — — 5.0 ns — — 5.0 ns -300 300 ps -300 300 ps S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

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... PJref t PLL output clock duty cycle PDuty t PLL output stable time PStal 1 Refer to Section 8.4, “Setting SYSCLK and PCLK” on page 43. S1D13742 X63A-A-001-06 PLL Stable 10 ms Lock In Time PLL xxMHz Output (xx = 44.26~66.95MHz) Time (ms) www.DataSheet.co.kr Figure 7-2: PLL Start-Up Time Table 7-2: PLL Clock Requirements Parameter Revision 6 ...

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... Epson Research and Development Vancouver Design Center 7.2 RESET# Timing RESET# CLKI Symbol t1 Active Reset Pulse Width Hardware Functional Specification Issue Date: 2007/09/ CLKI Figure 7-3 S1D13742 RESET# Timing Table 7-3 S1D13742 RESET# Timing Parameter www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 29 Min Max Units 1 — CLKI S1D13742 X63A-A-001-06 Datasheet pdf - http://www ...

Page 30

... Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-4: Intel 80 Input A.C. Characteristics - 1.8 Volt S1D13742 X63A-A-001-06 t wcs ast ...

Page 31

... Note 1 — ns Note 2 — ns — ns — ns — ns — ns — ns — — 4SYSCLK + 26 ns CL=30pF 5SYSCLK + 4SYSCLK + 8pF 5SYSCLK + 14 ns — ns CL=30pF — 8pF S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 32

... Data Port. Writes to the Memory Data Port will not increment the register address to support burst data writes to memory. Note 3: When CNF1=0, only MD[7:0] are used. When CNF1=1, MD[15:0] are used for accesses to the Memory Data Port. MD[7:0] are used for all other accesses. Figure 7-5: Intel 80 Input A.C. Characteristics - 3.3 Volt S1D13742 X63A-A-001-06 t wcs t ...

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... Note 1 — ns Note 2 — ns — ns — ns — ns — ns — ns — — 4SYSCLK + 21 ns CL=30pF 5SYSCLK + 4SYSCLK + 8pF 5SYSCLK + 11 ns — ns CL=30pF — 8pF S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 34

... A Volt EN IOVDD 0.8 IOVDD IOVDD ½ t pHZ Figure 7-6: Definition of Transition Time to Hi-Z State S1D13742 X63A-A-001-06 , delay time when a gate voltage of final stage of the Pch-MOSFET pHZ Internal logic delay + t (from High to Hi-Z) pHZ , delay time when a gate voltage of final stage of the Nch- pLZ Internal logic delay + t ...

Page 35

... Figure 7-7: Panel Timing Parameters Derived From (REG[16h] bits 6- (REG[18h] bits 6-0) REG[22h] bits 6-0 (REG[20h] bits 6-0) (REG[1Ch] bits 1-0, REG[1Ah] bits 7-0) REG[1Eh] bits 7-0 REG[26h] bits 7-0 REG[24h] bits 6-0 Revision 6.01 - EPSON CONFIDENTIAL Page 35 HNDP HSW Units Ts Lines (HT) S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 36

... LCD power-on sequence is activated by programming the Power Save Register (REG[56h]) bit 1 or bit ***LCD Signals include: VD[35:0], PCLK, HS, VS, and DE. Figure 7-8: TFT Power-On Sequence Timing Table 7-7: TFT Power-On Sequence Timing Symbol t1 Power Save Mode disabled to LCD signals active S1D13742 X63A-A-001-06 t1 Parameter www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development ...

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... Figure 7-9: TFT Power-Off Sequence Timing Table 7-8: TFT Power-Off Sequence Timing Symbol t1 Power Save Mode enabled to LCD signals low Hardware Functional Specification Issue Date: 2007/09/18 Parameter www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 37 t1 Min Max Units S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 38

... t10 t11 PCLK REG[28h] b7=1 t9 t10 t11 PCLK REG[28h] b7=0 VD[17:0] VD[35:0] Note HS, VS, PCLK all have Polarity Select bits via registers S1D13742 X63A-A-001- t18 t5 t6 t12 www.DataSheet.co.kr t12 invalid Note: 1 pixel/clock Mode invalid Note: 2 pixels/clock Mode Figure 7-10: 18/36-Bit TFT A.C. Timing Revision 6 ...

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... Lines VSW — Lines HPS — Ts — Ts HSW — Ts — Ts HDISP — Ts HPS — Ts — — Ts — — Ts — — Ts — — Ts — — Ts — — Ts — — Ts — — Ts VPS — Ts VNDP — Ts S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 40

... Page 40 8 Clocks 8.1 Clock Descriptions Internal PLL Enable PLL MHz CLKI External Clock Source CLKOUTEN CLKOUT Figure 8-1: S1D13742 Clock Block Diagram S1D13742 X63A-A-001-06 Clock Source Select (REG[12h] bit 0) Glitch Free 1 0 Divider • • • 32 PCLK Divide Select (REG[12h] bits 7-3) ...

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... Hardware Functional Specification Issue Date: 2007/09/ REG[08h] REG[0Ah] PFD CP VCO RS TCK REG[0Ah] CS REG[0Ch] REG[08h] V-Divider N-Counter REFCK www.DataSheet.co.kr MUX Figure 8-2: PLL Block Diagram Revision 6.01 - EPSON CONFIDENTIAL Page 41 VCP AMON MUX MUX SYSCLK 1/32 TOUT S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 42

... Function Register Read/Write Memory Read/Write Look-Up Table Register Read/Write Power Save LCD Output Note Register access does not require an internal clock as the S1D13742 creates a clock from the bus cycle alone. S1D13742 X63A-A-001-06 Internal Clock Requirements Internal SYSCLK Internal PCLK No Yes ...

Page 43

... Intel 80 Interface. < 22.594ns SYSCLK < 66.95MHz SYSCLK so that the desired PCLK frequency, f SYSCLK www.DataSheet.co.kr SysClk PCLK Frequency (MHz) Revision 6.01 - EPSON CONFIDENTIAL Page 43 PCLK = 47.5ns. BBC SysClk/3 SysClk S1D13742 X63A-A-001-06 , Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 44

... Page 44 9 Registers This section discusses how and where to access the S1D13742 registers. It also provides detailed information about the layout and usage of each register. Burst data writes to the register space is supported. This applies to all register write access except the Memory Data Port (REG[48h - 49h]) and the Gamma Correction Table Data Register [REG[54h]) ...

Page 45

... Epson Research and Development Vancouver Design Center 9.2 Register Set The S1D13742 registers are listed in the following table. Register REG[00h] Revision Code Register REG[04h] PLL M-Divider Register REG[08h] PLL Setting Register 1 REG[0Ch] PLL Setting Register 3 REG[10h] REG[14h] Panel Type Register REG[18h] Horizontal Non-Display Period Register (HNDP) ...

Page 46

... Bits marked as n/a have no hardware effect. Unless specified otherwise, all register bits are set to 0 during power-on reset. 9.3.1 Read-Only Configuration Registers REG[00h] Revision Code Register Default = 80h for S1D13742B00 or 81h for S1D13742B01 7 6 bits 7-2 Product Code bits [5:0] These are read-only bits that indicates the product code ...

Page 47

... Table 9-2: PLL M-Divide Selection REG[04h] bits 5-0 0h 01h 02h 03h • • • 20h 21h to 3Fh Hardware Functional Specification Issue Date: 2007/09/18 M-Divider bits 5 M-Divide Ratio 1:1 www.DataSheet.co.kr 2:1 3:1 4:1 • • • 33:1 Reserved Revision 6.01 - EPSON CONFIDENTIAL Page 47 Read/Write S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 48

... REG[0Ah] PLL Setting Register 2 Default = 00h 7 6 This register must be programmed with the value 28h. REG[0Ch] PLL Setting Register 3 Default = 00h 7 6 This register must be programmed with the value 00h. S1D13742 X63A-A-001-06 PLL Setting Register 0 bits 7 PLL Setting Register 1 bits 7 ...

Page 49

... REG[04] (MHz) bits 5 0Bh 60 12 0Bh www.DataSheet.co.kr • • • 53 19.2 12h 60 19.2 12h n Revision 6.01 - EPSON CONFIDENTIAL Page 49 Read/Write M-Divide PLLCLK POUT (MHz) Ratio (MHz) 12:1 1.0 53 12:1 1.0 60 • • • 19:1 1.0105 53.53 19:1 1.0105 60.63 Read/Write S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 50

... PCLK Divide Select bits [5:0] These bits specify the divide ratio for the panel clock (PCLK). The clock source for PCLK is SYSCLK. All resulting clock frequencies will maintain a 50/50 duty cycle regardless of divide ratio. REG[0012h] bits 7-3 S1D13742 X63A-A-001- Table 9-4 PCLK Divide Ratio Selection ...

Page 51

... The display memory or the Gamma Correction Table must not be accessed before this time. REG[04h] bit 7, the PLL Lock Bit, can be used to determine if the PLL output is stable. Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 51 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 52

... These bits specify the horizontal non-display period in pixels. For 36-bit wide panels, there are 2 pixels per external PCLK. HNDP is calculated using the following formula. HNDP = (REG[18h] bits 6-0) Note The minimum Horizontal Non-Display Period is 3 Pixels (REG[18h] bits 6-0 = 03h). HS Start + HS Width <= HNDP S1D13742 X63A-A-001-06 n Horizontal Display Period bits 6-0 ...

Page 53

... Vertical Non-Display Period bits 7 Pulse Width bits 6 Revision 6.01 - EPSON CONFIDENTIAL Read/Write 2 1 Read/Write Vertical Display Height bits 9 Read/Write Read/Write 2 1 X63A-A-001-06 Page S1D13742 ...

Page 54

... Default = 00h PCLK Polarity 7 6 bit 7 PCLK Polarity When this bit = 0, the PCLK outputs data transitions on the rising edge When this bit = 1, the PCLK outputs data transitions on the falling edge S1D13742 X63A-A-001-06 HS Pulse Start Position bits 6 Pulse Width bits 5-0 5 ...

Page 55

... In 16-bpp mode the entire 768K Byte display buffer is available and therefore the maxi- mum display resolution ≤ 768KB Hardware Functional Specification Issue Date: 2007/09/ Revision 6.01 - EPSON CONFIDENTIAL Read/Write Input Data Format X63A-A-001-06 Page 55 0 S1D13742 ...

Page 56

... For further information on Input Data Format and Memory Data Format, see Section 11, “Intel 80, 8-bit Interface Color Formats” on page 75, Section 12, “Intel 80, 16-bit Inter- face Color Formats” on page 78 and Section 13, “YUV Timing” on page 83. S1D13742 X63A-A-001-06 Table 9-5: Input Data Type Selection ...

Page 57

... U data = REG[30h] bits 7-0, original V data Original U data, V data = REG[032h] bits 7 data = REG[30h] bits 7-0, V data = REG[32h] bits 7-0 Reserved Revision 6.01 - EPSON CONFIDENTIAL Read/Write n Read/Write YUV/RGB Transfer Mode bits 2 S1D13742 X63A-A-001-06 Page ...

Page 58

... These bits specify the YUV/RGB Transfer mode. Recommended settings are provided for various specifications. Table 9-8: YUV/RGB Transfer Mode Selection REG[2Eh] bits 2-0 000 001 010 011 100 101 (Default) 110 111 S1D13742 X63A-A-001-06 Table 9-7: YUV Data Type Selection YRC Input Data Range ≤ ≤ 255 ≤ ≤ -128 ...

Page 59

... The V Data Input of YUV/RGB Converter data is fixed to the value of these bits. Hardware Functional Specification Issue Date: 2007/09/18 U Data Fix bits 7 Data Fix bits 7 Revision 6.01 - EPSON CONFIDENTIAL Read/Write 2 1 Read/Write X63A-A-001-06 Page S1D13742 ...

Page 60

... Window SwivelView Mode Select bits [1:0] These bits select different SwivelView™ orientations: Table 9-9: SwivelView™ Mode Select Options REG[34h] bits 1-0 Note All windows written to the active display can have independent rotation as the rotation is performed prior to writing to the display buffer. S1D13742 X63A-A-001-06 n SwivelView Orientation 00 0° ...

Page 61

... Single buffered window with no double buffering anywhere on the display. Use this to write a single buffered window while preventing tearing in a previously defined double buffered window. Reserved Use this to write data to be double buffered. Revision 6.01 - EPSON CONFIDENTIAL Page 61 Read/Write Window Pixel Sizing bits 1 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 62

... REG[36h] Bit 7 REG[36h] Bit S1D13742 X63A-A-001-06 Table 9-11: Window Data Type Selection Use Case Single buffered window with no double buffering anywhere on the display. Use this to write a single buffered window while preventing tearing in a previously defined double buffered window. www.DataSheet.co.kr Reserved Use this to write data to be double buffered ...

Page 63

... Write a new pixel doubled window. Hardware Functional Specification Issue Date: 2007/09/18 Table 9-12: Window Pixel Sizing Result 00 No Resizing 01 Pixel Doubling 10 Pixel Halving 11 Reserved Display Original Window www.DataSheet.co.kr Pixel Doubled Window Figure 9-1: Sizing Example Revision 6.01 - EPSON CONFIDENTIAL Page 63 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 64

... These bits determine the Y start position of the window in relation to the top left corner of the displayed image. Even in a rotated orientation, the top left corner is still relative to the displayed image. Note When pixel doubling or pixel halving is enabled, these registers should be programmed with the pre-resized coordinates. S1D13742 X63A-A-001-06 Window X Start Position bits 7 ...

Page 65

... Window Y End Position bits 7 n Revision 6.01 - EPSON CONFIDENTIAL Read/Write 2 1 Read/Write Window X End Position bits 9 Read/Write Read/Write Window Y End Position bits 9 X63A-A-001-06 Page S1D13742 ...

Page 66

... Panel dimension registers must be set before writing any window data. Note Upon writing the last pixel in the defined window, this register will automatically point back to the first pixel in the window. Therefore there is no need to re-initialize the point- ers. S1D13742 X63A-A-001-06 Memory Data Port bits [7: ...

Page 67

... Hardware Functional Specification Issue Date: 2007/09/18 Memory Address bits 7 Memory Address bits 15 Revision 6.01 - EPSON CONFIDENTIAL Read/Write 2 1 Read/Write 2 1 Read/Write Memory Address bit 19- X63A-A-001-06 Page S1D13742 ...

Page 68

... The Gamma Correction Tables should not be accessed during display period as this will result in visual anomalies. All updates to the LUT’s should be performed during non- display period or when the LUT’s are disabled and not in use. S1D13742 X63A-A-001-06 Look-Up Table Access Mode bits 1-0 ...

Page 69

... Red and Blue LUT’s will be used. Hardware Functional Specification Issue Date: 2007/09/18 Gamma Correction Table Index bits 5 Gamma Correction Table Data bits 5 Revision 6.01 - EPSON CONFIDENTIAL Read/Write 2 1 Read/Write X63A-A-001-06 Page S1D13742 ...

Page 70

... When this bit = 0, the LCD panel output Vertical Non-Display Period. When this bit = 1, the LCD panel output Vertical Display Period. Note VNDP is defined as time between the last pixel on the last line of one frame to the first pixel on the first line of the next frame. S1D13742 X63A-A-001-06 n ...

Page 71

... TE Output Pin Function Select bits [1:0] Table 9-14: TE Output Pin Function Select REG[58h] bits 1 Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr TE Output Pin Function Reserved Horizontal Non-Display Period Vertical Non-Display Period HS OR’d with VS Revision 6.01 - EPSON CONFIDENTIAL Page 71 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 72

... When this bit = 1, the associated GPIO interrupt (GPIO_INT) is triggered on the positive edge. Once triggered, the GPIO_INT pin will toggle from The GPIO_INT pins is cleared (non-active state (0)) by clearing the associated GPIO Interrupt Status bit (REG[62]) S1D13742 X63A-A-001-06 GPIO4 GPIO3 ...

Page 73

... Edge Interrupt Edge Interrupt Trigger Trigger Trigger 2 1 Read/Write GPIO2 Interrupt GPIO1 Interrupt GPIO0 Interrupt Status Status Status Read/Write GPIO2 Pull-down GPIO1 Pull-down GPIO0 Pull-down Control Control Control 2 1 X63A-A-001-06 Page S1D13742 ...

Page 74

... Page 74 10 Frame Rate Calculation The following formula is used to calculate the display frame rate. Where: f PCLK HT VT Note For definitions of panel timing parameters, see Section 7.4, “Display Interface” on page 35. S1D13742 X63A-A-001-06 f PCLK FrameRate = ------------------------------- - ( ) × PClk frequency (Hz) = Horizontal Total = Horizontal Display Width + Horizontal Non-Display Period ...

Page 75

... B1, Bit 1 G1, Bit 4 G2, Bit 4 B1, Bit 0 G1, Bit 3 G2, Bit 3 www.DataSheet.co.kr Pixel n Revision 6.01 - EPSON CONFIDENTIAL Page 75 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 Pixel S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 76

... Bit 2 MD1 Bit 1 MD0 Bit 0 Note: The Data order is as follows, MSB = MD7, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 11-2: 18 bpp (R 6-bit, G 6-bit, B 6-bit), 262,144 colors S1D13742 X63A-A-001-06 R1, Bit 5 G1, Bit 5 R1, Bit 4 G1, Bit 4 R1, Bit 3 ...

Page 77

... Page 77 R2, Bit 7 B1, Bit 7 R2, Bit 6 B1, Bit 6 R2, Bit 5 B1, Bit 5 R2, Bit 4 B1, Bit 4 R2, Bit 3 B1, Bit 3 R2, Bit 2 B1, Bit 2 R2, Bit 1 B1, Bit 1 R2, Bit 0 B1, Bit 0 Pixel S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 78

... Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0 for Green data and MSB = Bit 4, LSB = Bit 0 for Red and Blue data. Figure 12-1: 16 bpp (R 5-bit, G 6-bit, B 5-bit), 65,536 colors S1D13742 X63A-A-001-06 R1, Bit 4 ...

Page 79

... R2, Bit 0 Bit 1 Bit 0 Pixel n Pixel Revision 6.01 - EPSON CONFIDENTIAL Page 79 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 80

... MD4 MD3 MD2 MD1 MD0 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 5, LSB = Bit 0. Figure 12-3: 18 bpp Mode 2 (R 6-bit, G 6-bit, B 6-bit), 262,144 colors S1D13742 X63A-A-001-06 Bit 15 G1, Bit 5 Bit 14 G1, Bit 4 Bit 13 ...

Page 81

... Revision 6.01 - EPSON CONFIDENTIAL Page 81 G2, Bit 7 G2, Bit 6 G2, Bit 5 G2, Bit 4 G2, Bit 3 G2, Bit 2 G2, Bit 1 G2, Bit 0 B2, Bit 7 B2, Bit 6 B2, Bit 5 B2, Bit 4 B2, Bit 3 B2, Bit 2 B2, Bit 1 B2, Bit 0 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 82

... MD4 MD3 MD2 MD1 MD0 Note: The Data order is as follows, MSB = MD15, LSB = MD0 and Picture Data is MSB = Bit 7, LSB = Bit 0. Figure 12-5: 24 bpp Mode 2 (R 8-bit, G 8-bit, B 8-bit), 16,777,216 colors S1D13742 X63A-A-001-06 G1, Bit 7 Bit 15 G1, Bit 6 Bit 14 Bit 13 G1, Bit 5 ...

Page 83

... V13 www.DataSheet.co.kr U21 U23 Even Line Y21 Y22 Y23 V21 V23 YUV 4:2:0 Odd Line Y11 Y12 Y13 U/V Even Line Y21 Y22 Y23 Figure 13-1: YUV Format Definition Revision 6.01 - EPSON CONFIDENTIAL Page 83 Y14 Y24 Y14 U/V Y24 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 84

... Page 84 13.1 YUV 4:2:2 with Intel 80, 8-bit Interface Figure 13-2: YUV 4:2:2 with Intel 80, 8-bit Interface 13.2 YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface Figure 13-3: YUV 4:2:0 ODD Line with Intel 80, 8-bit Interface S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center ...

Page 85

... Epson Research and Development Vancouver Design Center 13.3 YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface Figure 13-4: YUV 4:2:0 EVEN Line with Intel 80, 8-bit Interface Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 85 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 86

... Page 86 13.4 YUV 4:2:2 with Intel 80, 16-bit Interface Figure 13-5: YUV 4:2:2 with Intel 80, 16-bit Interface S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2007/09/18 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 87

... Epson Research and Development Vancouver Design Center 13.5 YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface Figure 13-6: YUV 4:2:0 ODD Line with Intel 80, 16-bit Interface Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 87 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 88

... Page 88 13.6 YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface Figure 13-7: YUV 4:2:0 EVEN Line with Intel 80, 16-bit Interface S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2007/09/18 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 89

... Blue Data 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 Note: Only the 6 LSB’s from each table are used to construct an 18-bit pixel. Figure 14-1: Look-Up Table Architecture Revision 6.01 - EPSON CONFIDENTIAL Page 89 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 90

... Write data to Gamma Correction Data Register (data value for Index “x+1”). • Continue until complete (64 positions). Even in the case of 5:6:5, all 64 positions of each RGB LUT must be programmed when using the auto-increment method. • Enable Gamma Correction. S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL ...

Page 91

... G n+1 5 ... B n+1 4 ... B n+1 3 ... B n+1 2 ... B n+1 1 ... B n+1 0 ... B n+1 5 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... B n S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 92

... VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 R 1 S1D13742 X63A-A-001-06 Table 15-2: 36-Bit Data Format (Swapped) Cycle Count ...

Page 93

... Revision 6.01 - EPSON CONFIDENTIAL Page 93 ... n 5 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... B n S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 94

... VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 R 0 S1D13742 X63A-A-001-06 Table 15-4: 18-Bit Data Format (Swapped) Cycle Count 2 3 Driven Low ...

Page 95

... S1D13742 can be independently rotated with respect to each other. 16.2 90° SwivelView™ The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13742 in the following sense: A–B–C–D. The display is refreshed in the following sense: B-D-A-C. physical memory ...

Page 96

... SwivelView™ The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13742 in the following sense: A–B–C–D. The display is refreshed in the following sense: D-C-B-A. physical memory ...

Page 97

... SwivelView™ The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13742 in the following sense: A–B–C–D. The display is refreshed in the following sense: C-A-D-B. physical memory ...

Page 98

... Page 98 17 Host Interface 17.1 Using the Intel 80 Interface Accessing the S1D13742 through the Intel 80 interface is a multiple step process. All Registers and Memory are accessed through register space. Note All Register accesses, except the Memory Data Port, are 8-bit only. If the Host in- terface is 16-bits wide, the lsb’ ...

Page 99

... Figure 17-2: Register Read Example Sequence Hardware Functional Specification Issue Date: 2007/09/18 CS# RD# Address Data Data bits 7-0 Write Write Write Write www.DataSheet.co.kr CS# RD# Address Data Data bits 7-0 Read Read Read Write Revision 6.01 - EPSON CONFIDENTIAL Data 4 Data 4 S1D13742 X63A-A-001-06 Page 99 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 100

... Page 100 17.1.3 New Window Aperture Write procedure The S1D13742 has a special procedure to minimize set-up accesses when bursting window data. 1. The panel dimension registers must be set before writing any Window data. 2. Perform an Address Write to point to the first Window Register (Window X Start Po- sition). 3. Perform eight “ ...

Page 101

... Epson Research and Development Vancouver Design Center Figure 17-3: Sequential Memory Write Example Sequence Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 101 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 102

... Memory Read Address Registers to increment, thereby supporting burst reads. Note To access the 2 msb’s for each 18-bit value, you must know the physical address as they are stored at different locations as compared to the lower 16-bits. S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development ...

Page 103

... LCD frame period Figure 18-1: Switching of Buffer Pointers Revision 6.01 - EPSON CONFIDENTIAL Page 103 Switch buffer pointers since a frame completed being updated in the last LCD frame period S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 104

... The main/background image is in Buffer 1. Buffer 2 is empty. in Buffer 1. Buffer 2 is written The data output to the LCD with video data. The data output comes entirely from Buffer 1. to the LCD comes entirely from Buffer 1. S1D13742 X63A-A-001-06 Buffer 1 Buffer 1 Background Background Output image ...

Page 105

... LCD frame period. • Only one window can be double buffered at a time. Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 105 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 106

... The designs described in this section are presented only as examples of how such interfaces might be implemented. 19.1 Overview The S1D13742 was designed to directly support the Sanyo LC13015 and requires no additional hardware and minimal programming. The S1D13742 register settings and electrical interface is described below. 19.1.1 Electrical Interface ...

Page 107

... Epson Research and Development Vancouver Design Center 19.1.2 S1D13742 Register Settings for 352x416 TFT Panel Note The registers listed below are only those associated with panel specific timing issues All other registers are not shown here. Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line ...

Page 108

... Note The above values are intended as examples. This example assumes that CLKI = 19.2MHz and that the PLL is used to generate SYSCLK. Actual settings can vary and still remain within the LCD panel timing requirements. S1D13742 X63A-A-001-06 Comment 5Fh Window X End Position = 351 ...

Page 109

... Epson Research and Development Vancouver Design Center 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel Note The registers listed below are only those associated with panel specific timing issues All other registers are not shown here. Note When a window is setup for YUV data, the data must always alternate between odd and even lines, starting with an odd line ...

Page 110

... Note The above values are intended as examples. This example assumes that CLKI = 12MHz and that the PLL is used to generate SYSCLK. Actual settings can vary and still remain within the LCD panel timing requirements. S1D13742 X63A-A-001-06 Comment 1Fh Window X End Position = 799 ...

Page 111

... Revision 6.01 - EPSON CONFIDENTIAL Page 111 ½IOVDD t aht ½IOVDD t csf t t csf wrh ½IOVDD ½IOVDD t dht ½IOVDD t aht t rc ½IOVDD ½IOVDD t rdh t odh S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 112

... Read hold time (See note) t ddt Read falling edge to Data driven (See note) SYSCLK = 48MHz, PCLK = 12MHz, CLKI = 12MHz 1. t min = long enough to satisfy t wrh 2. t min = long enough to satisfy t rdh S1D13742 X63A-A-001-06 Parameter Min 1.4 0.3 0.6 + twrl 1.3 + trdl 9.2 42.6 Note 1 0.1 42.6 122.1 + trdh 108 ...

Page 113

... For maximum 102.7 nsec CL=30pF 92.5 nsec For minimum CL=8pF 32.1 nsec 12.3 nsec S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 114

... t12 t10 t11 PCLK REG[28h] b7=1 t9 t12 t10 t11 PCLK REG[28h] b7=0 VD[17:0] VD[35:0] S1D13742 X63A-A-001- www.DataSheet.co.kr invalid Note: 1 pixel/clock Mode invalid Note: 2 pixels/clock Mode Figure 19-2: 18/36-Bit TFT A.C. Timing Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center t4 t8 ...

Page 115

... Max Units — ms — us 41.63 us — us — us — ns — us — ns — ns — ns — ns — ns — ns — ns — ns — ns S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 116

... Page 116 19.4 Example Play.exe Scripts The following example scripts are written for the PLAY.EXE program. The script Demo.txt will initialize the S1D13742, then display horizontal bars at different rotations, and then display a PIP+ window. Demo.txt verbose cmd:off out:on set:off halt 0 '============================================================================== ' _DEMO_.txt - Play script for 13742 to demonstrate various features. ...

Page 117

... Pause.txt ' PIP '---------------------------------------------------------- print "Draw Color bars in a PIP (small window)\n" SetWin.txt f WIN 0 DrawBarsA.txt DrawPIP.txt 50 50 100 128 Pause.txt section END Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 117 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 118

... LOOP S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 2007/09/18 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 119

... WIN $Color set $StartY ($StartY + $Lines) set $EndY ($EndY + $Lines) set $Color ($Color + 0821) set $Bars ($Bars - 1) if $Bars!=0 then goto LOOP Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 119 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 120

... LOOP Pause.txt verbose cmd:off out:on set:off halt 0 print "Paused . . . press any key to continue\n" input line S1D13742 X63A-A-001-06 $Width $Lines www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development Vancouver Design Center ...

Page 121

... SETWINDOW ' Change the register window settings ($SX >> $ ($SY >> $ ($EX >> $ ($EY >> 8) Hardware Functional Specification Issue Date: 2007/09/18 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Page 121 S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 122

... Page 122 19.5 References 19.5.1 Documents • Sanyo Electric Co., Ltd. Display Company, LC13015 Low Temperature P-Si TFT-LCD Specification, Document Number LC13015-040302 • Epson Research and Development, Inc., S1D13742 Hardware Functional Specification, Document Number X63A-A-001-xx. S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development ...

Page 123

... Optional, but recommended Figure 20-1: PLL Power Layout Revision 6.01 - EPSON CONFIDENTIAL Page 123 PLLVDD S1D13742 PLLVSS Typical Values: L1, L2 isolation bead C1 ~10uf bypass C2 1nf bypass C3 .1uf bypass Actual values may be different and subject to validation S1D13742 X63A-A-001-06 Datasheet pdf - http://www.DataSheet4U.net/ ...

Page 124

... Another solution might be to have the traces connect to the pad, but with thermal relief around the pad to break up the copper connection. Ultimately the board must also be manufacturable, so best effort is acceptable. S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL ...

Page 125

... Mechanical Data TOP VIEW A1 corner SIDE VIEW BOTTOM VIEW corner Figure 21-1: S1D13742 FCBGA 121-pin Package Hardware Functional Specification Issue Date: 2007/09/18 ±0.20 8.0 Die Size www.DataSheet.co.kr 0.75 0. 1011 Revision 6.01 - EPSON CONFIDENTIAL Page 125 ...

Page 126

... Page 126 109 144 A 2 Symbol max θ Figure 21-2: S1D13742 QFP20 144-pin Package S1D13742 X63A-A-001- 108 INDEX www.DataSheet.co.kr Dimension in Millimeters Min Nom Max — 20 — — 20 — — 22 — ...

Page 127

... Item Logo Specified Device Name Die Revision Code Package Type Process and Package Revision Code [Blank] Control Code Year of Manufacture Month of Manufacture W/F Lot No. JAPAN Figure 21-3: S1D13742 FCBGA 121-pin Package Marking Hardware Functional Specification Issue Date: 2007/09/18 Y Package Center Line 3.18 2. ...

Page 128

... Pin 1 Y’ (1) 2.0 (7) ( Package Center Line Item Logo Specified JAPAN Device Name Control Code Year of Manufacture Week of Manufacture W/F Lot No. Figure 21-4: S1D13742 QFP 144-pin Package Marking S1D13742 X63A-A-001-06 Y Package Center Line 8.0 0.3 (2) ( (9) (10) (11) (12) (13) (14 ...

Page 129

... Epson Research and Development Vancouver Design Center 22 References The following documents contain additional information related to the S1D13742. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. • S1D13742 Product Brief (X63A-C-001-xx) • ...

Page 130

... EPSON EUROPE ELECTRONICS GmbH HEADQUARTERS Riesstrasse 15 80992 Munich, GERMANY Phone: +49-89-14005-0 FAX: +49-89-14005-110 23.1 Ordering Information To order the S1D13742 Mobile Graphics Engine, contact the Epson sales representative in your area. S1D13742 X63A-A-001-06 ASIA EPSON (CHINA) CO., LTD. 23F, Beijing Silver Tower 2# North RD DongSanHuan ...

Page 131

... Gamma Correction Look-Up Table Architecture - correct typos in Figure change data from display buffers to 6 bit, change the multiplexers to 64 positions from 256 • section 19.1.3 S1D13742 Register Settings for 800x480 TFT Panel - correct typo in Table 19-3, change the REG[04h] value to 0Bh X63A-A-001-05 Revision 5.02 (Issued 2006/08/23) • ...

Page 132

... TFT Panel Timing - correct typos in figure 7-8 18/36-Bit TFT A/C Timing - change references to REG[2Ah] to REG[28h], change t17 reference to falling edge of VS, and in table 7-7 18/36-Bit TFT A/C Timing change PCLK edge references to “active” S1D13742 X63A-A-001-06 www.DataSheet.co.kr Revision 6.01 - EPSON CONFIDENTIAL Epson Research and Development ...

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