S1M8836 Samsung Semiconductor, Inc., S1M8836 Datasheet
S1M8836
Related parts for S1M8836
S1M8836 Summary of contents
Page 1
... IMT2000. Various program-controlled power down options as well as low supply voltage help the design of wireless cell phones having minimum power consumption. Using the Samsung's proprietary digital phase-locked-loop technique, the S1M8836/37 has a linear phase detector characteristic and can be used for very stable, low noise PLL's. Supply voltage can range from 2. ...
Page 2
... S1M8836/37 APPLICATIONS High-rate data-service cellular telephones (for CDMA) : S1M8836, S1M8837 High-rate data-service portable wireless communications : S1M8837 Other wireless communications systems ORDERING INFORMATION Device + S1M8836X01-G0T0 + S1M8837X01-G0T0 +: New Product 2 Package Operating Temperature 24-QFN-3.5 4.5 FRACTIONAL-N RF/INTEGER-N IF DUAL PLL -40 to +85C ...
Page 3
... RF_EN Phase Charge Detector Pump IF Prescaler - + IF Prescaler Programmable Control Counter IF N-Latch 2-Bit Control 20-Bit Shift Register IF R-Latch IF Reference Counter 12 IF_EN S1M8836/ DGND GND DATA 13 CLOCK 3 ...
Page 4
... PIN DIAGRAM DGND GND RF V RFa DD OSCin 4 OUT0 OUT1 S1M8836/ foLD RF_EN 24-QFN FRACTIONAL-N RF/INTEGER-N IF DUAL PLL DGND ...
Page 5
... Programmable CMOS output. Level of the output is controlled by W2[19] bit. 24 OUT0 O Programmable CMOS output. Level of the output is controlled by W2[18] bit. In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and tri-state. Descriptions IF and V IF and V IF RF. DD S1M8836/ ...
Page 6
... FRACTIONAL-N RF/INTEGER-N IF DUAL PLL EQUIVALENT CIRCUIT DIAGRAM CLOCK, DATA, LE OSCin f RF RF, f RF bias foLD S1M8836/37 6 ...
Page 7
... NOTE: These devices are ESD sensitive. These devices must be handled in an ESD protected environment. Symbol Value V 0 600 D T - -65 to +150 STG Pin No. ESD level All < 2000 All < 300 All < 800 S1M8836/37 Unit Unit ...
Page 8
... Characteristic Power supply voltage Power supply S1M8836 RF+IF current S1M8837 RF+IF S1M8836 RF+IF S1M8837 RF+IF IF only Power down current Digital Inputs: CLOCK, DATA and LE High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Reference Oscillator Input: OSC ...
Page 9
... Min. Typ. =V /2, - /2, + /2, -800 P =V /2, +800 P -100 +100 -800 +800 VP-0.5V -2 -0. 0.5 0.25 =3. =3.0V -15 =4.0V -10 -10 0.5 S1M8836/37 Max. Unit +2 2.5 GHz 1.0 GHz 520 MHz 40 MHz 10 MHz 0 dBm 0 dBm 0 dBm ...
Page 10
... S1M8836/37 ELECTRICAL CHARACTERISTICS (Continued) (V =3.0V, V =3.0V unless otherwise specified Characteristic Serial Data Control CLOCK Frequency CLOCK Pulse Width High CLOCK Pulse Width Low DATA Set Up Time to CLOCK Rising Edge DATA Hold Time after CLOCK Rising Edge LE Pulse Width CLOCK Rising Edge to LE Rising Edge ...
Page 11
... ECL switching level to drive the following ECL divider so that it can be normally operated even in a smaller input power less than -10dBm. The amplified VCO output signal is divided by the prescaler with a pre- determined divide ratio (div. 8/9/12/13 for S1M8836, div. 16/17/20/21 for S1M8837, div. 8/9 for IF), the N counter and the Fractional-N circuitry( comparison frequency of the PFD ...
Page 12
... The RF N counter can be configured as a fractional counter. The fractional-N counter is selected when the Frac-N_SEL bit becomes HIGH. In the fractional mode, the S1M8836 is capable of offering a continuous integer divide range from 25 to 1023 and the S1M8837 offering a continuous integer divide range from 49 to 2047. ...
Page 13
... Frac-N_SEL is HIGH. For proper use of the fractional mode, the user should be kept in mind that 1. A fractional number should be set in the range from -0.5 to 0.5 in step of 1/62976. 2. For S1M8836/7, R can be selected 1-3. The clock frequency fixed at 9.84MHz (=19.68MHz/2, R=2) is recommended for the - performances related to the fractional noise and power consumption ...
Page 14
... S1M8836/37 Programming Description The S1M8836/37 can be programmed via the serial bus interface. The interface is made of 3 functional signals: clock, data, and latch enable(LE). Serial data is moved into the 22-bit shift register on the rising edge of the clock. These data enters MSB first. When LE goes HIGH, data in the shift register is moved into one of the 4 latches (by the 2-bit control) ...
Page 15
... RF and IF power down Speedy_Lock mode voltage HIGH pin #23 voltage HIGH pin # charge pump positive slope IF PFD Lock Detector(LD), Test mode RF charge pump positive slope RF PFD RF counter reset RF power down RF Fractional-N RF; PLL mode mode selection 8X) is selected and otherwise to the S1M8836/37 15 ...
Page 16
... S1M8836/37 Programmable Reference Counter(W1[18:2]) If the Control Bit is 00, data is moved from the 22-bit shift register into the R-latch which sets the IF reference counter. Serial data format is shown in the table below. MSB IF_CTL_WORD[21:19 Program Code 15-Bit IF R Counter Division Ratio Division ratio : 3 to 32767(The divide ratios less than 3 are prohibited) Data are shifted in MSB first ...
Page 17
... If the Control Bits are 01(IF), 10, and 11(RF), data is transferred from the 22-bit shift register into the N/Frac- latch. N Counter consists of swallow counter(A counter; 3-bit for IF & S1M8836RF and 4-bit for S1M8837RF), main counter(B counter; 7-bit for S1M8836/37 RF and 12-bit for IF), and fractional counter(F counter; 17-bit for S1M8836/37 RF). Serial data format is shown below. ...
Page 18
... S1M8836/ Counter MSB RF_CP_WORD FoLD[21:18] [17:13 Program Code RF Main Counter Division Ratio (B Counter) RF_NB_ CNTR[12:6] ; for S1M8836/37 Division 6 Ratio( Division ratio : 3 to 127 (The division ratios less than 3 are prohibited) RF Swallow Counter Division Ratio (A Counter) RF_NA_CNTR[5:2] ; for S1M8836 ...
Page 19
... FRACTIONAL-N RF/INTEGER-N IF DUAL PLL RF Fractional Counter MSB RF_CTL_WORD[21:19] 21 Program Code RF Fractional Counter Value (F Counter) FRAC_ CNTR[18:2] ; for S1M8836/37 RF Counter Value ( 31488 -31488 Counter Value: -31488(2's complementary) to 31488 NOTE: For a negative integer, the counter value should be inputted as the corresponding 2's complementary binary code ...
Page 20
... S1M8836/37 Programmable PFD and Charge Pump IF Charge Pump Gain ( IF_CP_WORD; W2[18] ) Control Words Control bits IF_CP_WORD W2[18] RF Charge Pump Gain ( RF_CP_WORD; W3[17:14] ) Control Words Control bits RF_CP_WORD W3[17:14] Icpo ( A) W3[17] 50 100 200 250 400 450 800 Phase Detector Polarity ( RF_CP_WORD/IF_CP_WORD; W3[13]/W2[17] ) Depending on VCO characteristics, W2[17] and W3[13] bits should be set as follows : ...
Page 21
... W1[20]) become HIGH. The control register and R/N counters, however, remains active for permitting serial programming and is capable of loading and latching in data during the power down. There are synchronous and asynchronous power-down modes for S1M8836/37. The power-down bit W1[19] is used to select between synchronous and asynchronous power-down. Synchronous power-down mode occurs if W1[19] bit is HIGH and then the power down bit (W4[20] or W1[20]) becomes HIGH ...
Page 22
... S1M8836/37 IF Power down mode table W1[20 Programmable Counter Reset Control Control Words Control bits IF_CTL_WORD W1[21] RF_CTL_WORD W4[21] Counter Reset mode resets R & N counters. RF Fractional-N selection Control Words Control bits RF_CTL_WORD W4[19] CMOS Output Control Control Words Control bits CMOS W2[21] W2[20] W2[19] In the Speedy Lock mode, the OUT0 and OUT1 pins can be utilized as synchronous switches between active low and a tri-state. The Speedy Lock mode activates the OUT0 and OUT1 pins to be connected to GROUND with a low impedance(< ...
Page 23
... LOW. Lock Detector(LD) There is analog mode for S1M8836/37. The foLD bits, W3[21:18], are used to select the lock detection mode and to output the selected lock signal through the foLD pin. The foLD output becomes HIGH with narrow pulsed LOW while both RF and IF PLLs are locked and thereby the output should be low-pass filtered for a DC locked voltage HIGH ...
Page 24
... VCO : External VCO output frequency f OSC : External reference frequency(From external oscillator) R: Preset divide ratio of programmable R counter (RF 3(typically 2), IF 32767); P: Preset modulus of quadruple modulus prescaler (S1M8836 RF:P=8, S1M8837 RF:P=16, IF:P=8) B: Preset value of main counter (S1M8836/37 RF 127, IF 4095) A: Preset value of swallow counter division ratio (S1M8836 RF ...
Page 25
... Phase Detector and Charge Pump Characteristics Phase difference detection Range : -2 When the positive-slope polarity of PFD is selected, W2[17]=HIGH or W3[13]=HIGH > fp DATA[20] DATA[10] DATA[ < < fp LSB CTL[1] CTL[ CWH t CLE fr < fp S1M8836/37 t LEW 25 ...
Page 26
... SIMPLIFIED SCHEMATIC DIAGRAM FOR RF SENSITIVITY TEST RF Signal 10dB ATTN Generator Frequency Counter Sensitivity limit is determined when the error of the divided RF output (foLD) becomes 10Hz. = 1.0GHz 100 S1M8836 Integer-N test mode f VCO f = 2.1GHz 210 16 S1M8837 Integer-N test mode Typical Application Example VCO 26 50 ...
Page 27
... R in 1000pF 56pF IF Out 56pF VCO C13 V P 100pF 0. 100pF 0. OUT0 24 OUT1 DGND 100pF V P R13 100pF R11 C12 C11 S1M8836/37 0 0. ...
Page 28
... The S1M8836/37 has external four power supply pins to supply on-chip bias, each for analog and digital blocks of RF and IF PLLs. Basically in doing PCB layout important that power supply lines should be separated from one another and thus coupling noises through the voltage supply lines can be minimized ...
Page 29
... FRACTIONAL-N RF/INTEGER-N IF DUAL PLL PACKAGE DIMENSIONS A 2X 0.10 #1 INDEX AREA 3.50 + 0.10 4X0.50 + 0.10 (0.05) #24 20X0.50 24X0.30 2X1.00 C 0.10 1.00MAX 0.27 + 0.05 0. MARK S1M8836/37 29 ...