IDT6116 Integrated Device Technology, Inc., IDT6116 Datasheet
IDT6116
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IDT6116 Summary of contents
Page 1
... All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clocks or refreshing for operation. The IDT6116SA/LA is packaged in 24-pin 600 and 300 mil plastic or ceramic DIP, 24-lead gull-wing SOIC, and 24-lead J-bend SOJ providing high board-level packing densities. ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Pin Configurations P24 P24 D24 D24 SO24 SO24 GND 12 DIP/SOIC/SOJ Top View Pin Description Name I GND (1) Truth Table ...
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... MAX, 6.42 3 Parameter Min. Typ. Supply Voltage 4.5 5.0 Ground 0 0 Input High Voltage 2.2 3.5 (1) ____ Input Low Voltage -0.5 +0.5V. CC IDT6116SA IDT6116LA Min. Max. Min. ____ ____ 10 ____ 5 ____ ____ ____ 10 ____ 5 ____ ____ ____ 0.4 2.4 ____ 2.4 6116SA25 6116SA35 6116LA20 ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) DC Electrical Characteristics (V = 5.0V ± 10 0.2V Symbol Parameter Power I Operating Power Supply CC1 SA Current, CS < Outputs Open Max Dynamic Operating CC2 SA Current, CS < Outputs Open LA ( Max MAX I Standby Power Supply ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Low V Data Retention Waveform 4.5V t CDR Test Conditions Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load DATA OUT 255Ω Figure 1. AC Test Load Military, Commercial, and Industrial Temperature Ranges DATA RETENTION MODE ≥ ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) AC Electrical Characteristics Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t Chip Select Access Time ACS (3) Chip Select to Output in Low-Z t CLZ t Output Enable to Output Valid OE (3) Output Enable to Output in Low-Z t OLZ (3) Chip Dese lect to Output in High-Z ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Timing Waveform of Read Cycle No. 1 ADDRESS OE CS DATA OUT Supply Currents I SB Timing Waveform of Read Cycle No. 2 ADDRESS DATA PREVIOUS DATA VALID OUT Timing Waveform of Read Cycle No DATA OUT NOTES HIGH for Read cycle. ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) AC Electrical Characteristics Symbol Parameter Write Cycle t Write Cycle Time WC t Chip Select to End-of-Write CW t Address Valid to End-of-Write AW t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR (3) Write to Output in High-Z ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) ADDRESS DATA PREVIOUS DATA VALID OUT DATA IN Timing Waveform of Write Cycle No. 2 (CS Controlled Timing) ADDRESS DATA IN NOTES must be HIGH during all address transitions. ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Ordering Information — Military IDT 6116 XX XXX Device Type Power Speed Ordering Information — Commercial & Industrial IDT 6116 XX XXX Device Type Power Speed Military, Commercial, and Industrial Temperature Ranges X X Package Process/ Temperature Range ...
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... IDT6116SA/LA CMOS Static RAM 2K (16K x 8-Bit) Datasheet Document History 1/7/ Pg. 11 08/09/00 02/01/01 12/30/03 Pg. 3,10 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. Military, Commercial, and Industrial Temperature Ranges Updated to new format ...