MD18R3268AG0 Samsung Semiconductor, Inc., MD18R3268AG0 Datasheet - Page 5

• Manufacturer Part Number: MD18R3268AG0
• Description: Description = MD18R3268AG0 (32Mx18)x8(16)pcs RIMM(TM) Module Based on 576Mb A-die, 32s Banks,32K/32ms Ref, 2.5V ;; Density(MB) = 512 ;; Organization = 128Mx36 ;; Component Composition = 576M(2th)x8 ;; Voltage(V) = 2.5 ;; Refresh = 32K/32ms ;; Speed(M
• Manufacturer: Samsung Semiconductor, Inc.

MD18R3268(G)AG0
CTM_THRU_R
CTMN_THRU_L
CTMN_THRU_R
DQA8_THRU_L..
DQA0_THRU_L
DQA8_THRU_R..
DQA0_THRU_R
DQB8_THRU_L..
DQB0_THRU_L
DQB8_THRU_R..
DQB0_THRU_R
ROW2_THRU_L..
ROW0_THRU_L
ROW2_THRU_R..
ROW0_THRU_R
SCK_THRU_L
SCK_THRU_R
SIN_THRU
Signal
A54
B12
A56
A4, B4, A6, B6, A8, B8,
A10, B10, A12
B67, A67, B65, A65, B63,
A63, B58, A58, B56
B32, A32, B30, A30, B28,
A28, B26, A26, B24
A36, B36, A38, B38, A40,
B40, A42, B42, A44
B16, A18, B18
A52, B50, A50
A2
A71
B34
Module Connector Pads
Table 3: Module Connector Pad Description (Continued)
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
V
V
V
Type
RSL
RSL
RSL
RSL
RSL
RSL
RSL
RSL
RSL
CMOS
CMOS
CMOS
Page 4
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Positive polarity.
Clock To Master. Connects to left RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
Clock To Master. Connects to right RDRAM device on "Thru"
Channel. Interface clock used for transmitting RSL signals to the
controller. Negative polarity.
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to left RDRAM device on "Thru" Channel.
DQA8_THRU_L is non-functional on modules with x16 RDRAM
devices.
"Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to right RDRAM device on "Thru" Channel.
DQA8_THRU_R is non-functional on modules with x16 RDRAM
devices.
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to left RDRAM device on "Thru" Channel.
DQB8_THRU_L is non-functional on modules with x16 RDRAM
devices.
"Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or
write data between the controller and RDRAM devices on “Thru”
Channel. Connects to right RDRAM device on "Thru" Channel.
DQB8_THRU_R is non-functional on modules with x16 RDRAM
devices.
Row bus. 3-bit bus containing control and address information for
row accesses. Connects to left RDRAM device on "Thru" Channel.
Row bus. 3-bit bus containing control and address information for
row accesses. Connects to right RDRAM device on "Thru" Chan-
nel.
Serial Clock input. Clock source used to read from and write to
"Thru" Channel RDRAM control registers. Connects to left
RDRAM device on "Thru" Channel.
Serial Clock input. Clock source used to read from and write to
"Thru" Channel RDRAM control registers. Connects to right
RDRAM device on "Thru" Channel.
"Thru" Channel Serial I/O for reading from and writing to the con-
trol registers. Attaches to SIO0 of right RDRAM device on "Thru"
Channel.
32 Bit RIMM
Description
Version 0.1 Sept. 2003
Preliminary
®
Module