AD9832 Analog Devices, AD9832 Datasheet - Page 3

• Manufacturer Part Number: AD9832
• Description: CMOS Complete DDS
• Manufacturer: Analog Devices

REV. A
TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
*See Pin Function Descriptions.
Guaranteed by design but not production tested.
1
2
3
4
5
6
7
8
9
10
11
11A
*
FSYNC
SDATA
SCLK
Limit at
T
(B Version)
40
16
16
50
20
20
15
20
SCLK – 5
15
5
8
8
MIN
to T
MAX
PSEL0, PSEL1
t
7
D15
FSELECT
(V
DD
MCLK
= +3.3 V
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
D14
t
6
VALID DATA
Figure 4. Control Timing
t
5
Figure 3. Serial Timing
Figure 2. Master Clock
10%; +5 V
MCLK
t
4
Test Conditions/Comments
MCLK Period
MCLK High Duration
MCLK Low Duration
SCLK Period
SCLK High Duration
SCLK Low Duration
FSYNC to SCLK Falling Edge Setup Time
FSYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge
FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge
t
11
–3–
D2
t
2
VALID DATA
t
1
10%; AGND = DGND = 0 V, unless otherwise noted)
t
t
3
9
D1
t
10
D0
t
t
8
11A
VALID DATA
D15
D14
AD9832