AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 10

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AT94K05AL

Manufacturer Part Number
AT94K05AL
Description
Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
Manufacturer
ATMEL Corporation
Datasheet

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RAM
10
AT94K Series FPSLIC
Figure 7. Some Single Cell Modes
There are two types of RAM in the FPSLIC device: the FreeRAM distributed through the
FPGA Core and the SRAM shared by the AVR and FPGA. The SRAM is described in
“FPGA/AVR Interface and System Control” on page 21. The 32 x 4 dual-ported FPGA Fre-
eRAM blocks are dispersed throughout the array and are connected in each sector as shown
in Figure 8. A four-bit Input Data bus connects to four horizontal local buses (Plane 1) distrib-
uted over four sector rows. A four-bit Output Data bus connects to four horizontal local buses
(Plane 2) distributed over four sector rows. A five-bit Input-address bus connects to five verti-
cal express buses in the same sector column (column 3). A five-bit Output-address bus
connects to five vertical express buses in the same column. WAddr (Write Address) and
RAddr (Read Address) alternate positions in horizontally aligned RAM blocks. For the left-
Synthesis Mode
Arithmetic Mode
DSP/Multiplier Mode
Counter Mode
Tri-State/Mux Mode
CARRY IN
A
B
C
D
A
B
C
EN
C
D
C
A
B
A
B
D Q
D Q
D Q
D Q
Q (Registered)
and/or
PRODUCT
and/or
and/or
Q
SUM
or
SUM (Registered)
CARRY
PRODUCT (Registered)
or
CARRY
and/or
CARRY
Q
Q
Rev. 1138F–FPSLI–06/02

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