AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 100

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

TCNT1
Timer/Counter1 Read
100
AT94K Series FPSLIC
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the
CPU and the data of the high byte TCNT1H is placed in the TEMP register. When the CPU
reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register.
Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read
operation.
The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and
write a ccess . If Timer/Co un ter1 is w ritte n to a nd a clock sou rce is se le cted , th e
Timer/Counter1 continues counting in the timer clock-cycle after it is preset with the written
value.
Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL
Timer/Counter1 Output Compare Register – OCR1BH AND OCR1BL
The output compare registers are 16-bit read/write registers.
The Timer/Counter1 Output Compare Registers contain the data to be continuously compared
with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Con-
trol and Status register. A compare match does only occur if Timer/Counter1 counts to the
OCR value. A software write that sets TCNT1 and OCR1A or OCR1B to the same value does
not generate a compare match.
A compare match will set the compare interrupt flag in the CPU clock cycle following the com-
pare event.
Since the Output Compare Registers – OCR1A and OCR1B – are 16-bit registers, a tempo-
rary register TEMP is used when OCR1A/B are written to ensure that both bytes are updated
simultaneously. When the CPU writes the high byte, OCR1AH or OCR1BH, the data is tempo-
rarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL or OCR1BL,
the TEMP register is simultaneously written to OCR1AH or OCR1BH. Consequently, the high
byte OCR1AH or OCR1BH must be written first for a full 16-bit register write operation.
The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and
also interrupt routines perform access to registers using TEMP, interrupts must be disabled
during access from the main program and interrupt routines.
Bit
$2B ($4B)
$2A ($4A)
Read/Write
Initial Value
Bit
$29 ($49)
$28 ($48)
Read/Write
Initial Value
15
MSB
7
R/W
R/W
0
0
15
MSB
7
R/W
R/W
0
0
14
6
R/W
R/W
0
0
14
6
R/W
R/W
0
0
13
5
R/W
R/W
0
0
13
5
R/W
R/W
0
0
12
4
R/W
R/W
0
0
12
4
R/W
R/W
0
0
11
3
R/W
R/W
0
0
11
3
R/W
R/W
0
0
10
2
R/W
R/W
0
0
10
2
R/W
R/W
0
0
9
1
R/W
R/W
0
0
9
1
R/W
R/W
0
0
8
LSB
0
R/W
R/W
0
0
Rev. 1138F–FPSLI–06/02
8
LSB
0
R/W
R/W
0
0
OCR1AH
OCR1AL
OCR1BH
OCR1BL